sp804.inc

ARM9基于WINDOWSCE的BSP源代码

;
;   The content of this file or document is CONFIDENTIAL and PROPRIETARY
;   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
;   License Agreement between Licensee and Jade Technologies Co., Ltd.
;   restricting among other things, the use, reproduction, distribution
;   and transfer.  Each of the embodiments, including this information 
;   and any derivative work shall retain this copyright notice.
; 
;   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
;   All rights reserved.
;
; ----------------------------------------------------------------
; File:     sp804.inc,v
; Revision: 1.0
; ----------------------------------------------------------------
; $
;

; sp804.inc - Timer definition header file

    IF :LNOT: :DEF: SP804_INC
SP804_INC           EQU     1

; Timer offsets within a timer bank
TIMER0_OFFSET       EQU (0x00)
TIMER1_OFFSET       EQU (0x20)

; Individual timer bases
PHYS_TIMER0_BASE    EQU (PHYS_CT_BASE + TIMER0_OFFSET)
PHYS_TIMER1_BASE    EQU (PHYS_CT_BASE + TIMER1_OFFSET) 
PHYS_TIMER2_BASE    EQU (PHYS_CT2_BASE + TIMER0_OFFSET)
PHYS_TIMER3_BASE    EQU (PHYS_CT2_BASE + TIMER1_OFFSET) 

; Timer peripheral register definition
TIMER_Load                      EQU     (0x00)      ; counter decrements from this value - and resets counters
TIMER_Value                     EQU     (0x04)      ; current value of decrementing counter
TIMER_Control                   EQU     (0x08)      ; control register
TIMER_InterruptClear            EQU     (0x0C)      ; any write to here clears interupt output from counter
TIMER_RawInterruptStatus        EQU     (0x10)      ; [0] TimerXRIS Read Raw interrupt status from the counter
TIMER_MaskedInterruptStatus     EQU     (0x14)      ; [0] TimerXMIS Read Enabled interrupt status from the counter
TIMER_BackgroundLoadValue       EQU     (0x18)      ; counter decrements from this value - no reset of counters

; Dual Timer peripheral register definition
Timer0Load          EQU     (TIMER0_OFFSET + TIMER_Load)
Timer0Value         EQU     (TIMER0_OFFSET + TIMER_Value)
Timer0Control       EQU     (TIMER0_OFFSET + TIMER_Control)
Timer0IntClr        EQU     (TIMER0_OFFSET + TIMER_InterruptClear)
Timer0RIS           EQU     (TIMER0_OFFSET + TIMER_RawInterruptStatus)
Timer0MIS           EQU     (TIMER0_OFFSET + TIMER_MaskedInterruptStatus)
Timer0BGLoad        EQU     (TIMER0_OFFSET + TIMER_BackgroundLoadValue)

Timer1Load          EQU     (TIMER1_OFFSET + TIMER_Load)
Timer1Value         EQU     (TIMER1_OFFSET + TIMER_Value)
Timer1Control       EQU     (TIMER1_OFFSET + TIMER_Control)
Timer1IntClr        EQU     (TIMER1_OFFSET + TIMER_InterruptClear)
Timer1RIS           EQU     (TIMER1_OFFSET + TIMER_RawInterruptStatus)
Timer1MIS           EQU     (TIMER1_OFFSET + TIMER_MaskedInterruptStatus)
Timer1BGLoad        EQU     (TIMER1_OFFSET + TIMER_BackgroundLoadValue)

TimerPeriphID0      EQU     0xFE0       ;/* Peripheral ID register bits [7:0]   */
TimerPeriphID1      EQU     0xFE4       ;/* Peripheral ID register bits [15:8]  */
TimerPeriphID2      EQU     0xFE8       ;/* Peripheral ID register bits [23:16] */
TimerPeriphID3      EQU     0xFEC       ;/* Peripheral ID register bits [31:24] */

TimerPCellID0       EQU     0xFF0       ;/* PrimeCell ID register bits [7:0]    */
TimerPCellID1       EQU     0xFF4       ;/* PrimeCell ID register bits [15:8]   */
TimerPCellID2       EQU     0xFF8       ;/* PrimeCell ID register bits [23:16]  */
TimerPCellID3       EQU     0xFFC       ;/* PrimeCell ID register bits [31:24]  */

;Timer Control register
TIMER_ENABLE                EQU     (0x80)          ; [7] - if zero then timer module disabled
TIMER_INT_ENABLE            EQU     (0x20)          ; [5] - if zero then no interupt generated
TIMER_MODE_PERIODIC         EQU     (0x40)          ; [6] - if zero then free running
TIMER_MODE_32BIT            EQU     (0x02)          ; [1] - if zero then 16 bit mode
TIMER_MODE_ONESHOT          EQU     (0x01)          ; [0] - if zero then counter in wrapping mode

TIMER_RESERVED_MASK         EQU     (0xFFFFFF10)    ; [31:8][4] keep reserved bits

TIMER_PRE_Div1              EQU     (0x00)          ; [3:2] 00  Clock div 1
TIMER_PRE_Div16             EQU     (0x04)          ; [3:2] 01  Clock div 16
TIMER_PRE_Div256            EQU     (0x08)          ; [3:2] 10  Clock div 256


    ENDIF   ; SP804_INC
    
    END