dma.h

ARM9基于WINDOWSCE的BSP源代码

/*
*   The content of this file or document is CONFIDENTIAL and PROPRIETARY
*   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
*   License Agreement between Licensee and Jade Technologies Co., Ltd.
*   restricting among other things, the use, reproduction, distribution
*   and transfer.  Each of the embodiments, including this information 
*   and any derivative work shall retain this copyright notice.
* 
*   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
*   All rights reserved.
 * ----------------------------------------------------------------
 * File:     dma.h,v
 * Revision: 1.0
 * ----------------------------------------------------------------
 * $
 */
#include <winioctl.h>

#ifndef	__DMA_H__
#define __DMA_H__

#define MAX_DMA_CHANNELS	8
#define MAX_DMA_TRANSFER_SIZE	(PAGE_SIZE - 1)


// These are the burst size ids
#define BURST_SIZE_1	0x000
#define BURST_SIZE_4	0x001
#define BURST_SIZE_8	0x002
#define BURST_SIZE_16	0x003
#define BURST_SIZE_32	0x004
#define BURST_SIZE_64	0x005
#define BURST_SIZE_128	0x006
#define BURST_SIZE_256	0x007

// These are the transfer width ids
#define TRANSFER_WIDTH_BYTE		0x000
#define TRANSFER_WIDTH_WORD		0x001
#define TRANSFER_WIDTH_DWORD	0x002

// These are the flow control type ids
#define FLOW_MEM_MEM_DMAC		0x000	// Memory to memory - DMAC as flow controller
#define FLOW_MEM_PER_DMAC		0x001	// Memory to peripheral - DMAC as flow controller
#define FLOW_PER_MEM_DMAC		0x002	// Peripheral to memory - DMAC as flow controller
#define FLOW_PER_PER_DMAC		0x003	// Peripheral to peripheral - DMAC as flow controller
#define FLOW_PER_PER_DEST		0x004	// Peripheral to peripheral - destination peripheral as flow controller
#define FLOW_MEM_PER_DEST		0x005	// Memory to peripheral - destination peripheral as flow controller
#define FLOW_PER_MEM_SOURCE		0x006	// Peripheral to memory - source peripheral as flow controller
#define FLOW_PER_PER_SOURCE		0x007	// Peripheral to peripheral - source peripheral as flow controller


#define HAL_IOCTL_FUNCTION_BASE	2048	// The base function code for OEM HAL IOCTL functions

// The HAL IOCTL function list
#define HAL_IOCTL_ALLOCATE_DMA_CHANNEL		(HAL_IOCTL_FUNCTION_BASE + 0)
#define HAL_IOCTL_INITIALIZE_DMA_CHANNEL	(HAL_IOCTL_FUNCTION_BASE + 1)
#define HAL_IOCTL_FREE_DMA_CHANNEL			(HAL_IOCTL_FUNCTION_BASE + 2)
#define HAL_IOCTL_START_DMA_TRANSFER		(HAL_IOCTL_FUNCTION_BASE + 3)
#define HAL_IOCTL_HALT_DMA_TRANSFER			(HAL_IOCTL_FUNCTION_BASE + 4)
#define HAL_IOCTL_RESTART_DMA_TRANSFER		(HAL_IOCTL_FUNCTION_BASE + 5)
#define HAL_IOCTL_STOP_DMA_TRANSFER			(HAL_IOCTL_FUNCTION_BASE + 6)
#define HAL_IOCTL_GET_ERROR_STATUS			(HAL_IOCTL_FUNCTION_BASE + 7)
#define HAL_IOCTL_CLEAR_ERROR_STATUS		(HAL_IOCTL_FUNCTION_BASE + 8)
#define HAL_IOCTL_FREE_DMA_SYSINTR        (HAL_IOCTL_FUNCTION_BASE + 9)

// The HAL IOCTLs
#define IOCTL_HAL_ALLOCATE_DMA_CHANNEL	    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_ALLOCATE_DMA_CHANNEL, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_INITIALIZE_DMA_CHANNEL	CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_INITIALIZE_DMA_CHANNEL, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_FREE_DMA_CHANNEL		    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_FREE_DMA_CHANNEL, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_START_DMA_TRANSFER	    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_START_DMA_TRANSFER, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_HALT_DMA_TRANSFER		    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_HALT_DMA_TRANSFER, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_RESTART_DMA_TRANSFER	    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_RESTART_DMA_TRANSFER, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_STOP_DMA_TRANSFER		    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_STOP_DMA_TRANSFER, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_GET_ERROR_STATUS		    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_GET_ERROR_STATUS, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_CLEAR_ERROR_STATUS	    CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_CLEAR_ERROR_STATUS, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_HAL_FREE_DMA_SYSINTR          CTL_CODE(FILE_DEVICE_HAL, HAL_IOCTL_FREE_DMA_SYSINTR, METHOD_BUFFERED, FILE_ANY_ACCESS)

//
// Parameters for AllocateDMAChannel
//
typedef struct tagAllocateDMAParams {
	UCHAR	ucSourceDevice;
	UCHAR	ucDestDevice;
	UCHAR	ucPreferedPriority;
}ALLOCATE_DMA_PARAMS, *PALLOCATE_DMA_PARAMS;

//
// Result data for AllocateDMAChannel
//
typedef struct tagAllocateDMAResult {
	UCHAR	ucChannelNumber;
	DWORD	dwInterruptID;
}ALLOCATE_DMA_RESULT, *PALLOCATE_DMA_RESULT;

//
// Parameters for InitializeDMAChannel
//
typedef struct tagInitializeDMAParams {
	UCHAR	ucChannelNumber;
	UCHAR	ucSourceWidth;
	UCHAR	ucDestWidth;
	UCHAR	ucSourceBurstSize;
	UCHAR	ucDestBurstSize;
	UCHAR	ucFlowControl;
	BOOL	fIncrementSource;
	BOOL	fIncrementDest;
}INITIALIZE_DMA_PARAMS, *PINITIALIZE_DMA_PARAMS;

//
// Result data for InitializeDMAChannel
//
typedef struct tagInitializeDMAResult {
	UCHAR	ucPad;	// Keep the compiler happy
}INITIALIZE_DMA_RESULT, *PINITIALIZE_DMA_RESULT;

//
// Parameters for FreeDMAChannel
//
typedef struct tagFreeDMAParams {
	UCHAR	ucChannelNumber;
}FREE_DMA_PARAMS, *PFREE_DMA_PARAMS;

//
// Result data for FreeDMAChannel
//
typedef struct tagFreeDMAResult {
	UCHAR	ucPad;	// Keep the compiler happy
}FREE_DMA_RESULT, *PFREE_DMA_RESULT;

//
// Parameters for StartDMATransfer
//
typedef struct tagStartDMAParams {
	UCHAR	ucChannelNumber;
	PDWORD	pdwSourceBuffer;
	PDWORD	pdwDestBuffer;
	DWORD	dwTransferSize;
}START_DMA_PARAMS, *PSTART_DMA_PARAMS;

//
// Result data for StartDMATransfer
//
typedef struct tagStartDMAResult {
	UCHAR	ucPad;	// Keep the compiler happy
}START_DMA_RESULT, *PSTART_DMA_RESULT;

//
// Parameters for HaltDMATransfer
//
typedef struct tagHaltDMAParams {
	UCHAR	ucChannelNumber;
}HALT_DMA_PARAMS, *PHALT_DMA_PARAMS;

//
// Result data for HaltDMATransfer
//
typedef struct tagHaltDMAResult {
	UCHAR	ucPad;	// Keep the compiler happy
}HALT_DMA_RESULT, *PHALT_DMA_RESULT;

//
// Parameters for RestartDMATransfer
//
typedef struct tagRestartDMAParams {
	UCHAR	ucChannelNumber;
}RESTART_DMA_PARAMS, *PRESTART_DMA_PARAMS;

//
// Result data for RestartDMATransfer
//
typedef struct tagRestartDMAResult {
	UCHAR	ucPad;	// Keep the compiler happy
}RESTART_DMA_RESULT, *PRESTART_DMA_RESULT;

//
// Parameters for StopDMATransfer
//
typedef struct tagStopDMAParams {
	UCHAR	ucChannelNumber;
}STOP_DMA_PARAMS, *PSTOP_DMA_PARAMS;

//
// Result data for StopDMATransfer
//
typedef struct tagStopDMAResult {
	UCHAR	ucPad;	// Keep the compiler happy
}STOP_DMA_RESULT, *PSTOP_DMA_RESULT;

//
// Parameters for GetErrorStatus
//
typedef struct tagGetErrorStatusParams {
	UCHAR	ucPad;	// Keep the compiler happy
}GET_ERROR_PARAMS, *PGET_ERROR_PARAMS;

//
// Result data for GetErrorStatus
//
typedef struct tagGetErrorStatusResult {
	UCHAR	ucErrorStatus;
}GET_ERROR_RESULT, *PGET_ERROR_RESULT;

//
// Parameters for ClearErrorStatus
//
typedef struct tagClearErrorParams {
	UCHAR	ucErrorStatusMask;
}CLEAR_ERROR_PARAMS, *PCLEAR_ERROR_PARAMS;

//
// Result data for ClearErrorStatus
//
typedef struct tagClearErrorResult {
	UCHAR	ucPad;	// Keep the compiler happy
}CLEAR_ERROR_RESULT, *PCLEAR_ERROR_RESULT;

//
// Parameters for GetTCStatus
//
typedef struct tagGetTCStatusParams {
	UCHAR	ucPad;	// Keep the compiler happy
}GET_TC_PARAMS, *PGET_TC_PARAMS;

//
// Result data for GetTCStatus
//
typedef struct tagGetTCStatusResult {
	UCHAR	ucTCStatus;
}GET_TC_RESULT, *PGET_TC_RESULT;

//
// Parameters for ClearTCStatus
//
typedef struct tagClearTCParams {
	UCHAR	ucTCStatusMask;
}CLEAR_TC_PARAMS, *PCLEAR_TC_PARAMS;

//
// Result data for ClearTCStatus
//
typedef struct tagClearTCResult {
	UCHAR	ucPad;	// Keep the compiler happy
}CLEAR_TC_RESULT, *PCLEAR_TC_RESULT;

//
// Parameters for FreeDMASysintr
//
typedef struct tagFreeDMASysIntrParams {
	UCHAR	ucChannelNumber;
}FREE_DMA_SYSINTR_PARAMS, *PFREE_DMA_SYSINTR_PARAMS;

//
// Result data for FreeDMASysintr
//
typedef struct tagFreeDMASysIntrResult{
	UCHAR	ucPad; 	// Keep the compiler happy
}FREE_DMA_SYSINTR_RESULT, *PFREE_DMA_SYSINTR_RESULT;


#endif