platform.h

ARM9基于WINDOWSCE的BSP源代码

#define VA_GPIO0_OFFSET 				0x00024000         			/* GPIO 0 */
#define VA_GPIO1_OFFSET 				0x00025000         			/* GPIO 1 */
#define VA_GPIO2_OFFSET 				0x00026000         			/* GPIO 2 */
#define VA_GPIO3_OFFSET 				0x00027000         			/* GPIO 3 */
#define VA_GPIO4_OFFSET 				0x0002B000         			/* GPIO 4 */
#define VA_GPIO5_OFFSET 				0x0002C000         			/* GPIO 5 */
#define VA_GPIO6_OFFSET 				0x0002D000         			/* GPIO 6 */
#define VA_GPIO7_OFFSET 				0x0002E000         			/* GPIO 7 */
#define VA_GPIO8_OFFSET 				0x0002F000         			/* GPIO 8 */



#define VA_EDBG_BASE  					(VA_HDR_BASE + VA_EDBG_OFFSET)
#define VA_68KBUS_BASE					(VA_HDR_BASE + VA_68KBUS_OFFSET)           
#define VA_CT_BASE    					(VA_HDR_BASE + VA_CT_OFFSET)
#define VA_CT2_BASE   					(VA_HDR_BASE + VA_CT2_OFFSET)
#define VA_UART0_BASE 					(VA_HDR_BASE + VA_UART0_OFFSET)
#define VA_UART1_BASE 					(VA_HDR_BASE + VA_UART1_OFFSET)
#define VA_UART2_BASE 					(VA_HDR_BASE + VA_UART2_OFFSET)
#define VA_RTC_BASE   					(VA_HDR_BASE + VA_RTC_OFFSET)
#define VA_VIC_BASE   					(VA_HDR_BASE + VA_VIC_OFFSET)
#define VA_DMA_BASE   					(VA_HDR_BASE + VA_DMA_OFFSET)
#define VA_SC_BASE    					(VA_HDR_BASE + VA_SC_OFFSET)
#define VA_GPIO0_BASE 					(VA_HDR_BASE + VA_GPIO0_OFFSET)
#define VA_GPIO1_BASE 					(VA_HDR_BASE + VA_GPIO1_OFFSET)
#define VA_GPIO2_BASE 					(VA_HDR_BASE + VA_GPIO2_OFFSET)
#define VA_GPIO3_BASE 					(VA_HDR_BASE + VA_GPIO3_OFFSET)
#define VA_GPIO4_BASE 					(VA_HDR_BASE + VA_GPIO4_OFFSET)
#define VA_GPIO5_BASE 					(VA_HDR_BASE + VA_GPIO5_OFFSET)
#define VA_GPIO6_BASE 					(VA_HDR_BASE + VA_GPIO6_OFFSET)
#define VA_GPIO7_BASE 					(VA_HDR_BASE + VA_GPIO7_OFFSET)
#define VA_GPIO8_BASE 					(VA_HDR_BASE + VA_GPIO8_OFFSET)

/*
 *       VA 0x02100000 -> 0x03FFFFFF unused
 *       VA 0x04100000 -> 0x05FFFFFF unused
 */


/* -------------------------------------------------------------------------------
 *  Ethernet debug settings
 * -------------------------------------------------------------------------------
 */
 
// These settings must match config.bib
#define EDBG_PHYS_MEMORY_START      0x00010000
#define EDBG_MEMORY_START           (VA_RAM_BASE + EDBG_PHYS_MEMORY_START)
#define EDBG_MEMORY_SIZE            0x00020000



/* -------------------------------------------------------------------------------
 *  Z228 Interrupt Controller
 * -------------------------------------------------------------------------------
 */

/*  Interrupt numbers
 *  (refer to intx20t.c when making changes here.)
 */ 

/* The following mappings are for the VIC - on the chip */
#define IRQ_VIC_WDOG   											0
#define IRQ_VIC_SOFTINT											1
#define IRQ_VIC_CPUINT0											2      
#define IRQ_VIC_CPUINT1											3
#define IRQ_VIC_TIMER0 											4
#define IRQ_VIC_TIMER1 											4
#define IRQ_VIC_TIMER2 											5
#define IRQ_VIC_TIMER3 											5
#define IRQ_VIC_GPIO2  											6 
#define IRQ_VIC_IIC    											7
#define IRQ_VIC_CF     											8
#define IRQ_VIC_RTC    											9 
#define IRQ_VIC_USB    											10 
#define IRQ_VIC_UART0  											11  
#define IRQ_VIC_UART1  											12  
#define IRQ_VIC_UART2  											13
#define IRQ_VIC_UART3  											14
#define IRQ_VIC_SCI    											15
#define IRQ_VIC_CLCD1  											16  
#define IRQ_VIC_DMA    											17  
#define IRQ_VIC_PWRFAIL											18  
#define IRQ_VIC_SSP0   											19
#define IRQ_VIC_GPIO7  											20
#define IRQ_VIC_GPIO8_3											21
#define IRQ_VIC_KBD    											22
#define IRQ_VIC_AUDIO  											23
#define IRQ_VIC_CLCD0  											24
#define IRQ_VIC_GPIO8_5											25
#define IRQ_VIC_GPIO0  											26
#define IRQ_VIC_VIA    											27
#define IRQ_VIC_MP4D   											28
#define IRQ_VIC_MP4E   											29
#define IRQ_VIC_GPIO8_0											30
#define IRQ_VIC_GPIO8_1											31

/* The rest of these VIC mappings are Z228 specific */
#define IRQ_VIC_GND                        	32



// Markers for Start and End of VIC sourced IRQ's
#define IRQ_VIC_MIN     			IRQ_VIC_WDOG
#define IRQ_VIC_MAX     			IRQ_VIC_GPIO8_1

/* Unaltered SIC number */
//#define IRQ_SIC                            (IRQ_VIC_SIC - IRQ_VIC_MIN)

/* -------------------------------------------------------------------------------
 *  GPIO	Controller
 * -------------------------------------------------------------------------------
 */

//#define	GPIODATA						0x0                      
#define	GPIODIR								0x400
#define	GPIOIS								0x404
#define	GPIOIBE								0x408
#define	GPIOIEV								0x40c
#define	GPIOIE								0x410
#define	GPIORIS								0x414
#define	GPIOMIS								0x418
#define	GPIOIC								0x41c
#define	GPIOAFSEL							0x420
   


/* -------------------------------------------------------------------------------
 *  Serial debug baud rate
 * -------------------------------------------------------------------------------
 */
/* Top 16 bits is the integer divisor, bottom is the fraction divisor */
/* BAUD rates for a clock input of 			15.115MHz		16.375MHz			 32.75MHz			/*24MHz */
#ifdef	In_12MHz
#ifdef	Z228_133MHz
#define ARMVPB_BAUD_38400   	 	0x00180026 //    0x001A002A		// 0x00350013			// 0x00270004
#else		//Z228_266MHz
#define ARMVPB_BAUD_38400   	 	0x0031000d
#endif
#else	//In_13MHz
#ifdef	Z228_133MHz
#define ARMVPB_BAUD_38400   		0x001A002A
#else		//Z228_266MHz
#define ARMVPB_BAUD_38400   	 	0x00350013
#endif
#endif


#define BAUD_BRDI_MASK         	0xFFFF0000  /* Baud rate integer mask                           */
#define BAUD_BRDF_MASK          0x0000FFFF  /* Baud rate fractional mask                        */
#define BAUD_BRDI_SHIFTRIGHT    16          /* Shift required Integer baud to lower 16 bytes    */


/* -------------------------------------------------------------------------------
 * Timer/clock definitions
 * -------------------------------------------------------------------------------
 */
#define NUMSYSTIMERS    (sizeof(gSysTimers) / sizeof(gSysTimers[0]))

#define TIMER0              0
#define TIMER1              1

// Base Clock frequency (before any scaling)
#define CLOCK_BASE_FREQ     (PCLK/2)		//15115000  //32000  //1000000 
// Clock divisor applied to base frequency to prescale
#define CLOCK_PRESCALER     1		//(CLOCK_BASE_FREQ/1000000)

// The following can be used to scale the 1 msec timer and RTC appropriately -
// this is required for slow systems e.g. CPUs instantiated in FPGAs.
#define TIMERSCALE          1

// Clock frequency in Hertz (after prescaling)
#define OEM_CLOCK_FREQ      (CLOCK_BASE_FREQ / CLOCK_PRESCALER)
// Clock count required per millisecond
#define OEM_COUNT_1MS       (OEM_CLOCK_FREQ / 1000) * TIMERSCALE

// System tick (reschedule period) length in milliseconds
#define RESCHED_PERIOD      1
// Number of clock counts per system tick
#define RESCHED_INCREMENT   (OEM_COUNT_1MS * RESCHED_PERIOD)

// Maximum clock tick resolution (32-bit counter)
#define MAX_TICK_COUNT      0xffffffff
// Maximum number of milliseconds spent in idle
#define IDLE_MAX_MS         (MAX_TICK_COUNT / RESCHED_INCREMENT)

/* 
 * Timer used by the scheduler to determine when
 * to switch context and run threads.
 */
#define OS_TIMER                TIMER0
#define OS_TIMERINT             IRQ_VIC_TIMER1


#endif /* __platform_h */

/* EOF platform.h */