platform.h

ARM9基于WINDOWSCE的BSP源代码

/*
*   The content of this file or document is CONFIDENTIAL and PROPRIETARY
*   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
*   License Agreement between Licensee and Jade Technologies Co., Ltd.
*   restricting among other things, the use, reproduction, distribution
*   and transfer.  Each of the embodiments, including this information 
*   and any derivative work shall retain this copyright notice.
* 
*   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
*   All rights reserved.
 * ----------------------------------------------------------------
 * File:     platform.h,v
 * Revision: 1.0
 * ----------------------------------------------------------------
 * $
 * 
 *   Z228 address map
 * 
 * ***********************************************************************/

#ifndef __platform_h
#define __platform_h                    1

#include "cdefs.h"


/* -------------------------------------------------------------------------------
 *  System CLOCK
 * -------------------------------------------------------------------------------
 */ 

//There are some macros to need to be modified according to your target board hardware.

//#define VGA
#define QVGA
#define Z228_266MHz
//#define Z228_133MHz
#define In_12MHz
//#define In_13MHz


#ifdef	In_12MHz
	#define In_CLK						12092000				//12MHz
#else 
	#define In_CLK							13107200			//13MHz
#endif
//#define In_CLK						12092000			//12MHz

#ifdef	Z228_133MHz
	#define Z228_frq					(In_CLK*10)
#else 
#ifdef	Z228_266MHz	
	#define Z228_frq					(In_CLK*20)
#else
#endif

#endif


#define HCLK							(Z228_frq/2)
#define PCLK							(Z228_frq/4)





/* -------------------------------------------------------------------------------
 *  Physical memory / device address's 
 * -------------------------------------------------------------------------------
 */ 
#define PHYS_RAM_BASE      		0x00000000      /* SDRAM base address, Must be 0x0100 0000 boundary for MPMC */
#define PHYS_DMA_LIST_BASE 		0x03EE0000			/* DMA list base in SDRAM */
#define PHYS_CLCD_BUFF_BASE		0x03F00000      /* Frame Buffer in SDRAM */
                           		
#define PHYS_AACI_BASE     		0x20037000			/* Advanced Audio CODEC Interface */
#define PHYS_MMCI0_BASE    		0x20039000			/* MultiMedia Card Interface 0 */
#define PHYS_MMCI1_BASE    		0x2003B000			/* MMC Interface 1 */                       
#define PHYS_68KBUS_BASE			0x20004000
#define PHYS_ETHERNET_BASE 		PHYS_68KBUS_BASE     /* Ethernet */
#define PHYS_USB_BASE      		0x20080000		 	/* Universal Serial Bus */
#define PHYS_CF_BASE					0x2000E000
#define PHYS_SSMC_CNTL_BASE		0x2000F000		 	/* Synchronous Static Memory Controller */
#define PHYS_MPMC_CNTL_BASE		0x2000D000		 	/* MultiPort Memory Controller */
#define PHYS_CLCD_CNTL_BASE		0x20002000		 	/* Color LCD Controller */
#define PHYS_DMA_BASE      		0x20001000		 	/* Dynamic Memory Access Controller */
#define PHYS_DMA2_BASE     		0x20011000		 	/* Dynamic Memory Access Controller2 */
#define PHYS_VIA_BASE      		0x20012000		 	/* VIA Controller*/
#define PHYS_VIC_BASE      		0x20010000		 	/* Vectored Interrupt Controller */
#define PHYS_MP4D_BASE     		0x20000000		 	/* MPEG4 Decoder Controller */
#define PHYS_MP4E_BASE     		0x2000C000		 	/* MPEG4 Eecoder Controller */
#define PHYS_SC_BASE       		0x20020000		 	/* System Controller */
#define PHYS_WDOG_BASE     		0x20021000		 	/* Watchdog */
#define PHYS_CT_BASE       		0x20022000			/* Counter/Timers 0 & 1 */
#define PHYS_CT2_BASE      		0x20023000			/* Counter/Timers 2 & 3 */
#define PHYS_GPIO0_BASE    		0x20024000			/* General Purpose Input/Output 0 */
#define PHYS_GPIO1_BASE    		0x20025000			/* GPIO 1 */
#define PHYS_GPIO2_BASE    		0x20026000			/* GPIO 2 */
#define PHYS_GPIO3_BASE    		0x20027000			/* GPIO 3 */
#define PHYS_GPIO4_BASE    		0x2002B000			/* GPIO 4 */
#define PHYS_GPIO5_BASE    		0x2002C000			/* GPIO 5 */
#define PHYS_GPIO6_BASE    		0x2002D000			/* GPIO 6 */
#define PHYS_GPIO7_BASE    		0x2002E000			/* GPIO 7 */	
#define PHYS_GPIO8_BASE    		0x2002F000			/* GPIO 8 */
#define PHYS_RTC_BASE      		0x20028000		 	/* Real Time Clock */    
#define PHYS_SCI_BASE      		0x20038000			/* Smart Card 0 base */
#define PHYS_UART0_BASE    		0x20030000			/* Universal Asynchronous Receive/Transmit 0 Debug output*/ 
#define PHYS_UART1_BASE    		0x20031000			/* UART 1 */
#define PHYS_UART2_BASE    		0x20032000			/* UART 2 */
#define PHYS_UART3_BASE    		0x20033000			/* UART 3 */
#define PHYS_SSP_BASE      		0x20034000			/* Synchronous Serial Port0 */
#define PHYS_SSP1_BASE     		0x20035000			/* Synchronous Serial Port1 */
                           		
                           		
#define PHYS_FLASH_BASE    		0xC4000000      /* Flash memory */


/* -------------------------------------------------------------------------------
 *  Z228 Development Board Flash settings
 * -------------------------------------------------------------------------------
 */

// Z228 Development Board Flash programming enable bits
#define ARMVPB_FLASHPROG_FLWREN         BIT0

// The following settings are a reflection of those found in platform.inc
// They MUST be kept in sync.
#define ARMVPB_FLASH_SIZE           		SZ_32M
#define ARMVPB_FLASH_END               	(PHYS_FLASH_BASE + ARMVPB_FLASH_SIZE - 1)
#define ARMVPB_FLASH_BLOCK_SIZE        	SZ_128K   


/* -------------------------------------------------------------------------------
 * VIRTUAL ADDRESSES
 * -------------------------------------------------------------------------------
 *
 * The following are the virtual address mappings which have a 512Mb range and 
 *  are either positioned in the cached memory space from 0x80000000 to 0x9FFFFFFF 
 *  or, for devices, the uncached range of memory from 0xA0000000 to 0xBFFFFFFF. 
 * But the ranges are overlayed so that they share a 512Mb address range of
 *  0x00000000 to 0x1FFFFFFF (i.e. a mask of 0x1FFFFFFF is applied to the values 
 *  below).
 */

/*
 * System Flash
 *
 *      Virtual address range of 0x00000000 to 0x03FFFFFF (64Mb)
 */
#define VA_FLASH_BASE   			0x80000000             // Flash, 64Mb

/*
 * System RAM
 *
 * Allow space for the RAM to grow up 128Mb. NOTE, however, that we
 * can only declare RAM for the minimum amount of memory possible in
 * a system, because the kernel uses the very top of RAM for its own
 * structures
 *
 *      Virtual address range of 0x08000000 to 0x0FFFFFFF (128Mb)
 */
#define VA_RAM_BASE    				0x88000000               // RAM 128Mb

/*
 * ARM Color LCD
 *
 *      Virtual address range of 0x06000000 to 0x060FFFFF (1Mb)
 */
#define VA_CLCD_BUFF_BASE       	0xa6000000      	// Frame Buffer

/*
 *      VA 0x06100000 -> 0x07FFFFFF unused
 */

/*
 * Include entries for those devices which are (potentially) used in
 * the OAL
 */

/* Various devices and controllers
 *
 *      Virtual address range of 0x02000000 to 0x020FFFFF (1Mb)
 */
#define VA_HDR_BASE     				0xa2000000         		 	/* VP peripherals base, 1Mb */
                        				
#define VA_68KBUS_OFFSET				0x00004000          		/* M68K BUS */
#define VA_EDBG_OFFSET  				VA_68KBUS_OFFSET        /* Ethernet Debug */
                        				
#define VA_CT_OFFSET    				0x00022000		          /* Counter/Timers 0 & 1 */
#define VA_CT2_OFFSET   				0x00023000		          /* Counter/Timers 2 & 3 */
#define VA_UART0_OFFSET 				0x00030000		          /* UART 0 - affects entry in serial.reg */
#define VA_UART1_OFFSET 				0x00031000		          /* UART 1 - affects entry in serial.reg */
#define VA_UART2_OFFSET 				0x00032000		 					/* UART 2 */
#define VA_UART3_OFFSET 				0x00033000
#define VA_RTC_OFFSET   				0x00028000              /* Real-time clock */
#define VA_VIC_OFFSET   				0x00010000              /* Vectored Interrupt Controller */
#define VA_DMA_OFFSET   				0x00001000              /* Virtual address for DMA */
#define VA_VIA_BASE     				0x00012000		 					/* VIA Controller*/
#define VA_SC_OFFSET    				0x00020000              /* System Controller */