sp810.h

ARM9基于WINDOWSCE的BSP源代码

/*
*   The content of this file or document is CONFIDENTIAL and PROPRIETARY
*   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
*   License Agreement between Licensee and Jade Technologies Co., Ltd.
*   restricting among other things, the use, reproduction, distribution
*   and transfer.  Each of the embodiments, including this information 
*   and any derivative work shall retain this copyright notice.
* 
*   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
*   All rights reserved.
*/
// ----------------------------------------------------------------
// File:     sp810.h,v
// Revision: 1.0
// ----------------------------------------------------------------
// $ 
//

// sp810.h - System Controller

#ifndef sp810_h
#define sp810_h

// Structure to access SP810 hardware registers 

typedef volatile struct TAG_SP810_REGS 
{
    DWORD SCCTRL;           		/* 0x0 System Control register    */
    DWORD SCSYSSTAT;        	/* 0x4 System Status Register register   */
    DWORD RESERVED[62];
    DWORD TAPID;         		/* 0x100 JTAG ID register    */
    DWORD SYSOPT;         		/* 0x104System options bus register */
    DWORD EBITIMEOUT;          	/* 0x108 EBI Timeout value register */
    DWORD PINCONFIG;        	/* 0x10C Pin Mux Configuration register */
    DWORD RESETCFG;       		/* 0x110 Reset Configuration register */
    DWORD CLKGATED1;       	/* 0x114 Clock Gated Control register 0  */
    DWORD CLKGATED2;       	/* 0x118 Clock Gated Control register 1 */
    DWORD MEMCFG;          		/* 0x11C Memory Controller Configuration register */
    DWORD BOOTMAPCLR ;         	/* 0x120 TCM Configuration register */
    DWORD MAPMOVE;         	/* 0x124 TCM Configuration register */
    DWORD TCMSEL;         		/* 0x128 TCM Configuration register */
    DWORD BOOTSEL;       		/* 0x12C 24.3.15  Boot Select register */
    DWORD CLKCFG;       		/* 0x130 Peripheral Control register 0  */
    DWORD PLL0;       			/* 0x134 Peripheral Control register 1 */
    DWORD PLL1;          		/* 0x138 Peripheral Clock Enable register */
    DWORD PWRMAN;			/* 0x13C Peripheral Clock Enable register */
    DWORD ARMCFG;         		/* 0x140 Peripheral Clock Disable register */
    DWORD CLKSEL;       		/* 0x144 PLL Frequency Control register */
    DWORD CLCD0CLKSEL;       	/* 0x148 Peripheral Control register 0  */
    DWORD CLCD1CLKSEL;       	/* 0x150 Peripheral Control register 1 */

} vstSP810Regs, *pvstSP810Regs;

/*
 * Peripheral Clock Enable Signal definitions - used when enabling and
 * disabling peripheral clocks via the SP810 System Controller
 */
#define HCLKDMA     	0x00004000
#define HCLKSMC     	0x00600000
#define HCLKMPMC    	0x00000008
#define HCLKCLCD    	0x00000010
#define PCLKSSP     	0x00080000

#define PCLKUART0   	0x00018000
#define PCLKUART1   	0x00006000
#define PCLKUART2   	0x00001800

/*
 * The following should be renamed when the final peripheral set is defined
 * by the System Integrator.
 */
#define CLKBIT10    0x400
#define CLKBIT11    0x800
#define CLKBIT12    0x1000
#define CLKBIT13    0x2000
#define CLKBIT14    0x4000
#define CLKBIT15    0x8000
#define CLKBIT16    0x10000
#define CLKBIT17    0x20000
#define CLKBIT18    0x40000
#define CLKBIT19    0x80000
#define CLKBIT20    0x100000
#define CLKBIT21    0x200000
#define CLKBIT22    0x400000
#define CLKBIT23    0x800000
#define CLKBIT24    0x1000000
#define CLKBIT25    0x2000000
#define CLKBIT26    0x4000000
#define CLKBIT27    0x8000000
#define CLKBIT28    0x10000000
#define CLKBIT29    0x20000000
#define CLKBIT30    0x40000000
#define CLKBIT31    0x80000000

#endif // sp810_h