📄 pl011.h
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/*
* The content of this file or document is CONFIDENTIAL and PROPRIETARY
* to Jade Technologies Co., Ltd. It is subjected to the terms of a
* License Agreement between Licensee and Jade Technologies Co., Ltd.
* restricting among other things, the use, reproduction, distribution
* and transfer. Each of the embodiments, including this information
* and any derivative work shall retain this copyright notice.
*
* Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
* All rights reserved.
// ----------------------------------------------------------------
// File: pl011.h,v
// Revision: 1.1
// ----------------------------------------------------------------
// $
*/
#ifndef PL011_H_INCLUDED
#define PL011_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
/* Register offsets */
#define PL011_DR 0x00 /* Data register */
#define PL011_RSR 0x04 /* Receive status register (read) */
#define PL011_ECR 0x04 /* Error Clear register (write) */
#define PL011_FR 0x18 /* Flag register (read) */
#define PL011_ILPR 0x20 /* IrDA low-power counter register */
#define PL011_IBRD 0x24 /* Integer baud rate divisor register */
#define PL011_FBRD 0x28 /* Fractional baud rate divisor register */
#define PL011_LCR_H 0x2C /* Line control register, high byte */
#define PL011_CR 0x30 /* Control register */
#define PL011_IFLS 0x34 /* Interrupt FIFO level select register */
#define PL011_IMSC 0x38 /* Interrupt mask set/clear register */
#define PL011_RIS 0x3C /* Raw Interrupt status register (read) */
#define PL011_MIS 0x40 /* Masked interrupt status register (read) */
#define PL011_ICR 0x44 /* Interrupt clear register (write) */
#define PL011_DMACR 0x48 /* DMA Control register */
#define PL011_DR_MASK 0x00FF /* Data register, [08:11] are Status bits */
/* Receive status */
#define PL011_RSR_OE 0x08 /* Overrun error */
#define PL011_RSR_BE 0x04 /* Break error */
#define PL011_RSR_PE 0x02 /* Parity error */
#define PL011_RSR_FE 0x01 /* Framing error */
#define PL011_RSR_ALLERRORS 0x0F /* All errors */
/* Error clear */
#define PL011_ECR_ALLERRORS 0x0F /* All errors (used for clearing errors) */
/* NOTE: The value is not important */
/* Flag */
#define PL011_FR_RI 0x100 /* Ring indicator */
#define PL011_FR_TXFE 0x080 /* Transmit FIFO empty */
#define PL011_FR_RXFF 0x040 /* Receive FIFO full */
#define PL011_FR_TXFF 0x020 /* Transmit FIFO full */
#define PL011_FR_RXFE 0x010 /* Receive FIFO empty */
#define PL011_FR_BUSY 0x008 /* UART Busy */
#define PL011_FR_DCD 0x004 /* Data Carrier Detect */
#define PL011_FR_DSR 0x002 /* Data Set Ready */
#define PL011_FR_CTS 0x001 /* Clear To Send */
/* Line control (high byte) */
#define PL011_LCR_H_SPS 0x80 /* Stick Parity Select */
#define PL011_LCR_H_WLEN_8 0x60 /* Word length 8 bits */
#define PL011_LCR_H_WLEN_7 0x40 /* Word length 7 bits */
#define PL011_LCR_H_WLEN_6 0x20 /* Word length 6 bits */
#define PL011_LCR_H_WLEN_5 0x00 /* Word length 5 bits */
#define PL011_LCR_H_FEN 0x10 /* Enable FIFOs */
#define PL011_LCR_H_STP2 0x08 /* Two stop bits select */
#define PL011_LCR_H_EPS 0x04 /* Even Parity Select */
#define PL011_LCR_H_PEN 0x02 /* Parity Enable */
#define PL011_LCR_H_BRK 0x01 /* Send Break */
#define PL011_LCR_H_WLEN_MASK 0x60 /* Word length bits mask */
/* Control */
#define PL011_CR_CTSEN 0x8000 /* CTS Hardware Flow Enable */
#define PL011_CR_RTSEN 0x4000 /* RTS Hardware Flow Enable */
#define PL011_CR_OUT2 0x2000 /* Out2 (RI on DTE) */
#define PL011_CR_OUT1 0x1000 /* Out1 (DCD on DTE) */
#define PL011_CR_RTS 0x0800 /* Request To Send */
#define PL011_CR_DTR 0x0400 /* Data Transmit Ready */
#define PL011_CR_RXE 0x0200 /* Receive Enable */
#define PL011_CR_TXE 0x0100 /* Transmit Enable */
#define PL011_CR_LBE 0x0080 /* Loop Back Enable */
#define PL011_CR_SIRLP 0x0004 /* IrDA SIR low power mode */
#define PL011_CR_SIREN 0x0002 /* SIR Enable */
#define PL011_CR_UARTEN 0x0001 /* UART Enable */
/* Interrupt FIFO level select */
#define PL011_IFLS_RXIFLSEL_1_8 0x00 /* Rx Interrupt >= 1/8 */
#define PL011_IFLS_RXIFLSEL_1_4 0x08 /* Rx Interrupt >= 1/4 */
#define PL011_IFLS_RXIFLSEL_1_2 0x10 /* Rx Interrupt >= 1/2 */
#define PL011_IFLS_RXIFLSEL_3_4 0x18 /* Rx Interrupt >= 3/4 */
#define PL011_IFLS_RXIFLSEL_7_8 0x20 /* Rx Interrupt >= 7/8 */
#define PL011_IFLS_TXIFLSEL_1_8 0x0 /* Tx Interrupt <= 1/8 */
#define PL011_IFLS_TXIFLSEL_1_4 0x1 /* Tx Interrupt <= 1/4 */
#define PL011_IFLS_TXIFLSEL_1_2 0x2 /* Tx Interrupt <= 1/2 */
#define PL011_IFLS_TXIFLSEL_3_4 0x3 /* Tx Interrupt <= 3/4 */
#define PL011_IFLS_TXIFLSEL_7_8 0x4 /* Tx Interrupt <= 7/8 */
#define PL011_IFLS_RXIFLSEL_MASK 0x38 /* Rx interrupt FIFO level select mask */
#define PL011_IFLS_TXIFLSEL_MASK 0x07 /* Tx interrupt FIFO level select mask */
/* Interrupt mask set/clear */
#define PL011_IMSC_OEIM 0x400 /* Overrun error interrupt mask */
#define PL011_IMSC_BEIM 0x200 /* Break error interrupt mask */
#define PL011_IMSC_PEIM 0x100 /* Parity error interrupt mask */
#define PL011_IMSC_FEIM 0x080 /* Framing error interrupt mask */
#define PL011_IMSC_RTIM 0x040 /* Rx Timeout interrupt mask */
#define PL011_IMSC_TXIM 0x020 /* Tx interrupt mask */
#define PL011_IMSC_RXIM 0x010 /* Rx interrupt mask */
#define PL011_IMSC_DSRMIM 0x008 /* DSR modem interrupt mask */
#define PL011_IMSC_DCDMIM 0x004 /* DCD modem interrupt mask */
#define PL011_IMSC_CTSMIM 0x002 /* CTS modem interrupt mask */
#define PL011_IMSC_RIMIM 0x001 /* RI modem interrupt mask */
#define PL011_IMSC_ALLINTERRUPTS 0x07FF /* All interrupts */
/* Raw interrupt status */
#define PL011_RIS_OERIS 0x400 /* Overrun error interrupt raw state */
#define PL011_RIS_BERIS 0x200 /* Break error interrupt raw state */
#define PL011_RIS_PERIS 0x100 /* Parity error interrupt raw state */
#define PL011_RIS_FERIS 0x080 /* Framing error interrupt raw state */
#define PL011_RIS_RTRIS 0x040 /* Rx Timeout interrupt raw state */
#define PL011_RIS_TXRIS 0x020 /* Tx interrupt raw state */
#define PL011_RIS_RXRIS 0x010 /* Rx interrupt raw state */
#define PL011_RIS_DSRRMIS 0x008 /* DSR modem interrupt raw state */
#define PL011_RIS_DCDRMIS 0x004 /* DCD modem interrupt raw state */
#define PL011_RIS_CTSRMIS 0x002 /* CTS modem interrupt raw state */
#define PL011_RIS_RIRMIS 0x001 /* RI modem interrupt raw state */
/* Masked interrupt status */
#define PL011_MIS_OEMIS 0x400 /* Overrun error interrupt masked state */
#define PL011_MIS_BEMIS 0x200 /* Break error interrupt masked state */
#define PL011_MIS_PEMIS 0x100 /* Parity error interrupt masked state */
#define PL011_MIS_FEMIS 0x080 /* Framing error interrupt masked state */
#define PL011_MIS_RTMIS 0x040 /* Rx Timeout interrupt masked state */
#define PL011_MIS_TXMIS 0x020 /* Tx interrupt masked state */
#define PL011_MIS_RXMIS 0x010 /* Rx interrupt masked state */
#define PL011_MIS_DSRMMIS 0x008 /* DSR modem interrupt masked state */
#define PL011_MIS_DCDMMIS 0x004 /* DCD modem interrupt masked state */
#define PL011_MIS_CTSMMIS 0x002 /* CTS modem interrupt masked state */
#define PL011_MIS_RIMMIS 0x001 /* RI modem interrupt masked state */
/* Interrupt clear */
#define PL011_ICR_OEIC 0x400 /* Overrun rror interrupt clear */
#define PL011_ICR_BEIC 0x200 /* Break error interrupt clear */
#define PL011_ICR_PEIC 0x100 /* Parity error interrupt clear */
#define PL011_ICR_FEIC 0x080 /* Framing error interrupt clear */
#define PL011_ICR_RTIC 0x040 /* Rx Timeout interrupt clear */
#define PL011_ICR_TXIC 0x020 /* Tx interrupt clear */
#define PL011_ICR_RXIC 0x010 /* Rx interrupt clear */
#define PL011_ICR_DSRMIC 0x008 /* DSR modem interrupt clear */
#define PL011_ICR_DCDMIC 0x004 /* DCD modem interrupt clear */
#define PL011_ICR_CTSMIC 0x002 /* CTS modem interrupt clear */
#define PL011_ICR_RIMIC 0x001 /* RI modem interrupt clear */
#define PL011_ICR_ALLINTERRUPTS 0x07FF /* All interrupts */
/* DMA control */
#define PL011_DMACR_DMAONERR 0x4 /* DMA disable receive on error */
#define PL011_DMACR_TXDMAE 0x2 /* DMA transmit enable */
#define PL011_DMACR_RXDMAE 0x1 /* DMA receive enable */
/* FIFO buffer */
#define PL011_FIFO_DEPTH 16 /* FIFO buffer depth (in bytes) */
/* Tx and Rx interrupt, FIFO trigger levels */
#define PL011_IFLSEL_1_8 0x0 /* 000, 1/8 full */
#define PL011_IFLSEL_1_4 0x1 /* 001, 1/4 full */
#define PL011_IFLSEL_1_2 0x2 /* 010, 1/2 full */
#define PL011_IFLSEL_3_4 0x3 /* 011, 3/4 full */
#define PL011_IFLSEL_7_8 0x4 /* 100, 7/8 full */
#define PL011_IFLSEL_101 0x5 /* 101, reserved */
#define PL011_IFLSEL_110 0x6 /* 110, reserved */
#define PL011_IFLSEL_111 0x7 /* 111, reserved */
/* UART clock (in Hertz) */
#define PL011_CLK (PCLK/2) //15115000//12M //16375000;13M //32750000 if CPU_clk = 0x133MHz
/* Macros to calculate the real, integer and fractional parts of the baud rate divisor */
#define PL011_BAUD_DIV(baud) ((ULONG)(PL011_CLK * 4) / baud)
#define PL011_BAUD_DIVINT(baud) ((PL011_BAUD_DIV(baud) & 0xFFFFFFC0) >> 6)
#define PL011_BAUD_DIVFRAC(baud) ((PL011_BAUD_DIV(baud) & 0x0000003F) >> 0)
/* Limits for IBRD (integer part of the baud-rate divisor) */
#define PL011_IBRD_MIN 1 /* Minimum value */
#define PL011_IBRD_MAX 65535 /* Maximum value (then FBRD must be zero) */
#ifdef __cplusplus
}
#endif
#endif // PL011_H_INCLUDED
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