📄 pl190.inc
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; The content of this file or document is CONFIDENTIAL and PROPRIETARY
; to Jade Technologies Co., Ltd. It is subjected to the terms of a
; License Agreement between Licensee and Jade Technologies Co., Ltd.
; restricting among other things, the use, reproduction, distribution
; and transfer. Each of the embodiments, including this information
; and any derivative work shall retain this copyright notice.
;
; Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
; All rights reserved.
;
; ----------------------------------------------------------------
; File: pl190.inc,v
; Revision: 1.1
; ----------------------------------------------------------------
; $
;
; pl190.inc - Vectored Interrupt controller
IF :LNOT: :DEF: PL190_INC
PL190_INC EQU 1
; VIC register offsets
ARM_VICIRQStatus EQU (0x00) ; IRQ status register
ARM_VICFIQStatus EQU (0x04) ; FIQ status register
ARM_VICRawIntr EQU (0x08) ; Raw interrupt status register
ARM_VICIntSelect EQU (0x0C) ; Interrupt select register
ARM_VICIntEnable EQU (0x10) ; Interrupt enable register
ARM_VICIntEnClear EQU (0x14) ; Interrupt enable clear register
ARM_VICSoftInt EQU (0x18) ; Software interrupt register
ARM_VICSoftIntClear EQU (0x1C) ; Software interrupt clear register
ARM_VICProtection EQU (0x20) ; Protection enable register
ARM_VICVectAddr EQU (0x30) ; Vector address register
ARM_VICDefVectAddr EQU (0x34); ; Default vector address register
ENDIF ; PL190_INC
END
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