sp810.inc

ARM9基于WINDOWSCE的BSP源代码

;
;   The content of this file or document is CONFIDENTIAL and PROPRIETARY
;   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
;   License Agreement between Licensee and Jade Technologies Co., Ltd.
;   restricting among other things, the use, reproduction, distribution
;   and transfer.  Each of the embodiments, including this information 
;   and any derivative work shall retain this copyright notice.
; 
;   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
;   All rights reserved.
;
; ----------------------------------------------------------------
; File:     sp810.inc,v
; Revision: 1.0
; ----------------------------------------------------------------
; $ 
;

; sp810.inc - System Controller

    IF :LNOT: :DEF: SP810_INC
SP810_INC           EQU     1

; System Controller offsets		                        
ARM_SCCtrl              EQU     (0x00)      ; 0x0 System Control register   
ARM_SCSysStat           EQU     (0x04)      ; 0x4 System Status Register register                                                      
ARM_TAPID            		EQU     (0x100)     ; 0x100 JTAG ID register                        
ARM_SYSOPT            	EQU     (0x104)     ; 0x104System options bus register                 
ARM_EBITIMEOUT          EQU     (0x108)     ; 0x108 EBI Timeout value register                  
ARM_PINCONFIG           EQU     (0x10C)     ; 0x10C Pin Mux Configuration register         
ARM_RESETCFG          	EQU     (0x110)     ; 0x110 Reset Configuration register              
ARM_CLKGATED1          	EQU     (0x114)     ; 0x114 Clock Gated Control register 0         
ARM_CLKGATED2          	EQU     (0x118)     ; 0x118 Clock Gated Control register 1            
ARM_MEMCFG             	EQU     (0x11C)     ; 0x11C Memory Controller Configuration register
ARM_BOOTMAPCLR          EQU     (0x120)     ; 0x120 TCM Configuration register                
ARM_MAPMOVE          		EQU     (0x124)     ; 0x124 TCM Configuration register                
ARM_TCMSEL           		EQU     (0x128)     ; 0x128 TCM Configuration register               
ARM_BOOTSEL          		EQU     (0x12C)     ; 0x12C Boot Select register               
ARM_CLKCFG       				EQU     (0x130)     ; 0x130 Peripheral Control register 0                 
ARM_PLL0      					EQU     (0x134)     ; 0x134 Peripheral Control register 1                      
ARM_PLL1           			EQU     (0x138)     ; 0x138 Peripheral Clock Enable register              
ARM_PWRMAN							EQU     (0x13C)     ; 0x13C Peripheral Clock Enable register                 
ARM_ARMCFG             	EQU     (0x140)     ; 0x140 Peripheral Clock Disable register          
ARM_CLKSEL       				EQU     (0x144)     ; 0x144 PLL Frequency Control register                   
         
      
                   
; Bitfield designations ------------------------------------------
                   
; Peripheral Clock enable/disable bits 
                   
SCPerClkHclkDma         EQU     0x00004000	
SCPerClkHclkSmc        	EQU     0x00600000
SCPerClkMpmcClk         EQU     0x00000008      ; 'Normal' memory.. hopefully includes SDRAM
SCPerClkHclkClcd        EQU     0x00000010
SCPerClkPclkSsp         EQU     0x00080000			;

SCPerClkPclkUart0       EQU     0x00018000      ;CLDGATEED2                                               
SCPerClkPclkUart1       EQU     0x00006000			;CLDGATEED2                                                       
SCPerClkPclkUart2       EQU     0x00001800      ;CLDGATEED2                                                  


; The following defines the peripheral clock sources that are left enabled during the initial power down code.
; We leave the memory controllers and the keyboard/debug UART enabled.

SCPerClkEnPhase1        EQU     SCPerClkHclkSmc:OR:\
                                 SCPerClkMpmcClk
;                                SCPerClkPclkUart2

; This decides which peripheral clocks are left enabled when the platform
; goes to sleep - change this if you have other peripherals you need to leave
; clocked - for now we leave the keyboard/debug UART enabled.                            
SCPerClkEnPhase2        EQU     SCPerClkHclkSmc:OR:SCPerClkPclkUart2

; Defines the peripherals that should be enabled as the system starts
; Peripherals should be added or taken away from this as is applicable
SCPerClkEnStartup       EQU     SCPerClkHclkSmc:OR:SCPerClkHclkClcd:OR:SCPerClkMpmcClk:OR:\
                                SCPerClkPclkSsp:OR:\
                                SCPerClkPclkUart0:OR:SCPerClkPclkUart2:OR:\
                                SCPerClkPclkUart1

; Control reg ARM_SCCtrl   

; ModeCtrl 
SCCtrlSetDoze           EQU     0x01        ; System controller set'Doze' bitfield
SCCtrlSetSlow           EQU     0x02        ; System controller set'Slow' bitfield
SCCtrlSetNormal         EQU     0x04        ; System controller set'Normal' bitfield

PMSetIdle								EQU     0x01	    ; Power Management Configuration Registers set'Idle' bitfield
PWSetSleep							EQU     0x02        ; Power Management Configuration Registers set'Slow' bitfield
PWSetNormal							EQU     0x00        ; Power Management Configuration Registers set'Normal' bitfield
PWSetStop								EQU			0x03	    ; Power Management Configuration Registers set'Stop' bitfield
PWSetPLL								EQU			0x04	    ; Power Management Configuration Registers PLL adjust
; ModeStatus
SCCtrlStatusDoze        EQU     0x08        ; System controller 'Doze' status bitfield
SCCtrlStatusSlow        EQU     0x10        ; System controller 'Slow' status bitfield
SCCtrlStatusNormal      EQU     0x20        ; System controller 'Normal' status bitfield

SCCtrlModeCtrlMask      EQU     (SCCtrlSetDoze:OR:\
                                SCCtrlSetSlow:OR:\
                                SCCtrlSetNormal)

SCCtrlModeStatusMask    EQU     (SCCtrlStatusDoze:OR:\
                                SCCtrlStatusSlow:OR:\
                                SCCtrlStatusNormal)

SCCtrlRemapClrReq       EQU     0x00000100      ; [8] 
SCCtrlRemapStatus       EQU     0x00000200      ; [9]
                                                ; 
SCCtrlHClkDivSelMask    EQU     0x00007000      ; this has been extended bit [14:12], was [14:13]

SCCtrlTimer0EnSel       EQU     0x00008000      ; [15]
SCCtrlTimer0EnOv        EQU     0x00010000  

SCCtrlTimer1EnSel       EQU     0x00020000      ; [17]
SCCtrlTimer1EnOv        EQU     0x00040000  

SCCtrlTimer2EnSel       EQU     0x00080000      ; [19]
SCCtrlTimer2EnOv        EQU     0x00100000  

SCCtrlTimer3EnSel       EQU     0x00200000      ; [21]
SCCtrlTimer3EnOv        EQU     0x00400000  

; Status Reg  ARM_SCSysStat

SCSysStatMpmcnSmc       EQU     0x00000001      ; [0]
SCSysStatBatOk          EQU     0x00000002      ; [1]
SCSysResetStatusMask    EQU     0x0000003c      ; [5:2]

    ENDIF ; SP810_INC
    
    END