📄 dmakern.h
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/*
* The content of this file or document is CONFIDENTIAL and PROPRIETARY
* to Jade Technologies Co., Ltd. It is subjected to the terms of a
* License Agreement between Licensee and Jade Technologies Co., Ltd.
* restricting among other things, the use, reproduction, distribution
* and transfer. Each of the embodiments, including this information
* and any derivative work shall retain this copyright notice.
*
* Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
* All rights reserved.
* ----------------------------------------------------------------
* File: dmakern.h,v
* Revision: 1.0
* ----------------------------------------------------------------
* $
*/
#ifndef __DMAKERN_H__
#define __DMAKERN_H__
#ifndef MIN
#define MIN(x,y) ((x) < (y) ? (x) : (y))
#endif
#define DMAC_BASE VA_DMA_BASE
// The DMA list buffer must be a fixed area in RAM so that we know the physical address
// Addresses must match config.bib settings
// Flash and RAM images the same
// Virtual address
#define DMA_LIST_BUFFER_VIRT ((PHYS_DMA_LIST_BASE - PHYS_RAM_BASE) + VA_RAM_BASE)
// Physical address
#define DMA_LIST_BUFFER_PHYS (PHYS_DMA_LIST_BASE)
// As the list buffer is 128K we can only have 1024 entries of 16 bytes per channel (8 channels)
// With a Page Size of 4K, this gives us a 4MB max transfer size.
#define MAX_DMA_LIST_ENTRIES 1024
// DMA controller registers
typedef struct tagDMACRegisters {
DWORD DMACIntStatus; // DMAC_BASE
DWORD DMACIntTCStatus; // DMAC_BASE + 0x004
DWORD DMACIntTCClear; // DMAC_BASE + 0x008
DWORD DMACIntErrorStatus; // DMAC_BASE + 0x00C
DWORD DMACIntErrClr; // DMAC_BASE + 0x010
DWORD DMACRawIntTCStatus; // DMAC_BASE + 0x014
DWORD DMACRawIntErrorStatus; // DMAC_BASE + 0x018
DWORD DMACEnbldChns; // DMAC_BASE + 0x01C
DWORD DMACSoftBReq; // DMAC_BASE + 0x020
DWORD DMACSoftSReq; // DMAC_BASE + 0x024
DWORD DMACSoftLBReq; // DMAC_BASE + 0x028
DWORD DMACSoftLSReq; // DMAC_BASE + 0x02C
DWORD DMACConfiguration; // DMAC_BASE + 0x030
DWORD DMACSync; // DMAC_BASE + 0x034
DWORD Padding1[50]; // DMAC_BASE + 0x038
DWORD DMACC0SrcAddr; // DMAC_BASE + 0x100
DWORD DMACC0DestAddr; // DMAC_BASE + 0x104
DWORD DMACC0LLI; // DMAC_BASE + 0x108
DWORD DMACC0Control; // DMAC_BASE + 0x10C
DWORD DMACC0Configuration; // DMAC_BASE + 0x110
DWORD Padding2[3]; // DMAC_BASE + 0x114
DWORD DMACC1SrcAddr; // DMAC_BASE + 0x120
DWORD DMACC1DestAddr; // DMAC_BASE + 0x124
DWORD DMACC1LLI; // DMAC_BASE + 0x128
DWORD DMACC1Control; // DMAC_BASE + 0x12C
DWORD DMACC1Configuration; // DMAC_BASE + 0x130
DWORD Padding3[3]; // DMAC_BASE + 0x134
DWORD DMACC2SrcAddr; // DMAC_BASE + 0x140
DWORD DMACC2DestAddr; // DMAC_BASE + 0x144
DWORD DMACC2LLI; // DMAC_BASE + 0x148
DWORD DMACC2Control; // DMAC_BASE + 0x14C
DWORD DMACC2Configuration; // DMAC_BASE + 0x150
DWORD Padding4[3]; // DMAC_BASE + 0x154
DWORD DMACC3SrcAddr; // DMAC_BASE + 0x160
DWORD DMACC3DestAddr; // DMAC_BASE + 0x164
DWORD DMACC3LLI; // DMAC_BASE + 0x168
DWORD DMACC3Control; // DMAC_BASE + 0x16C
DWORD DMACC3Configuration; // DMAC_BASE + 0x170
DWORD Padding5[3]; // DMAC_BASE + 0x174
DWORD DMACC4SrcAddr; // DMAC_BASE + 0x180
DWORD DMACC4DestAddr; // DMAC_BASE + 0x184
DWORD DMACC4LLI; // DMAC_BASE + 0x188
DWORD DMACC4Control; // DMAC_BASE + 0x18C
DWORD DMACC4Configuration; // DMAC_BASE + 0x190
DWORD Padding6[3]; // DMAC_BASE + 0x194
DWORD DMACC5SrcAddr; // DMAC_BASE + 0x1A0
DWORD DMACC5DestAddr; // DMAC_BASE + 0x1A4
DWORD DMACC5LLI; // DMAC_BASE + 0x1A8
DWORD DMACC5Control; // DMAC_BASE + 0x1AC
DWORD DMACC5Configuration; // DMAC_BASE + 0x1B0
DWORD Padding7[3]; // DMAC_BASE + 0x1B4
DWORD DMACC6SrcAddr; // DMAC_BASE + 0x1C0
DWORD DMACC6DestAddr; // DMAC_BASE + 0x1C4
DWORD DMACC6LLI; // DMAC_BASE + 0x1C8
DWORD DMACC6Control; // DMAC_BASE + 0x1CC
DWORD DMACC6Configuration; // DMAC_BASE + 0x1D0
DWORD Padding8[3]; // DMAC_BASE + 0x1D4
DWORD DMACC7SrcAddr; // DMAC_BASE + 0x1E0
DWORD DMACC7DestAddr; // DMAC_BASE + 0x1E4
DWORD DMACC7LLI; // DMAC_BASE + 0x1E8
DWORD DMACC7Control; // DMAC_BASE + 0x1EC
DWORD DMACC7Configuration; // DMAC_BASE + 0x1F0
DWORD Padding9[891]; // DMAC_BASE + 0x1F4
DWORD DMACPeriphID0; // DMAC_BASE + 0xFE0
DWORD DMACPeriphID1; // DMAC_BASE + 0xFE4
DWORD DMACPeriphID2; // DMAC_BASE + 0xFE8
DWORD DMACPeriphID3; // DMAC_BASE + 0xFEC
DWORD DMACCellID0; // DMAC_BASE + 0xFF0
DWORD DMACCellID1; // DMAC_BASE + 0xFF4
DWORD DMACCellID2; // DMAC_BASE + 0xFF8
DWORD DMACCellID3; // DMAC_BASE + 0xFFC
}DMAC_REGS, *PDMAC_REGS;
// DMA controller channel registers
typedef struct tagDMAChannelRegs {
DWORD DMACCxSrcAddr; // Channel base + 0x00
DWORD DMACCxDestAddr; // Channel base + 0x04
DWORD DMACCxLLI; // Channel base + 0x08
DWORD DMACCxControl; // Channel base + 0x0C
DWORD DMACCxConfiguration; // Channel base + 0x10
}DMAC_CHANNEL_REGS, *PDMAC_CHANNEL_REGS;
typedef struct tagLLIEntry *PLLI_ENTRY;
// LLI list entry structure
typedef struct tagLLIEntry {
DWORD dwSourceAddress;
DWORD dwDestAddress;
PLLI_ENTRY pNextEntry;
DWORD dwControl;
}LLI_ENTRY, *PLLI_ENTRY;
//
// DMA channel information
//
typedef struct tagDMAChannelInfo {
PDMAC_CHANNEL_REGS pDMACChannelRegs;
UCHAR ucSourceDevice;
UCHAR ucDestDevice;
UCHAR ucSourceWidth;
UCHAR ucDestWidth;
UCHAR ucSourceBurstSize;
UCHAR ucDestBurstSize;
UCHAR ucFlowControl;
BOOL fInUse;
BOOL fIncrementSource;
BOOL fIncrementDest;
BOOL fPowerDown;
DWORD dwTransferSize;
PDWORD pdwSourceBuffer;
PDWORD pdwDestBuffer;
DWORD dwDMASysIntr; // System Interrupt assignment
PLLI_ENTRY pPrevLLIEntry;
PLLI_ENTRY pNextLLIEntry;
PLLI_ENTRY pNextLLIEntryPhys;
}DMA_CHANNEL_INFO, *PDMA_CHANNEL_INFO;
//
// DMA subsystem information
//
typedef struct tagDMAInfo {
DMA_CHANNEL_INFO DMAChannels[MAX_DMA_CHANNELS];
}DMA_INFO, *PDMA_INFO;
// Currently allocated SYSINTR
typedef DWORD DMA_GLOB_SYSINTR;
// Register bit definitions
// DMAC configuration register bit masks
#define DMAC_CONFIG_E 0x0001 // DMA controller enable
#define DMAC_CONFIG_M1 0x0002 // Master 1 endianess
#define DMAC_CONFIG_M2 0x0004 // Master 2 endianess
// DMAC LLI register bit masks
#define DMAC_LLI_LM 0x0001 // Master select - set to access LLIs via AHB2, clear for AHB1
// DMAC channel control register bit masks
#define DMAC_CTRL_I 0x80000000 // Terminal count interrupt enable
#define DMAC_CTRL_CACHE 0x40000000 // Cacheable
#define DMAC_CTRL_BUF 0x20000000 // Bufferable
#define DMAC_CTRL_PRIV 0x10000000 // Privileged
#define DMAC_CTRL_DI 0x08000000 // Destination increment
#define DMAC_CTRL_SI 0x04000000 // Source increment
#define DMAC_CTRL_D 0x02000000 // Dest master select
#define DMAC_CTRL_S 0x01000000 // Source master select
#define DMAC_DWIDTH 0x00E00000 // Destination width
#define DMAC_SWIDTH 0x001C0000 // Source width
#define DMAC_DBSIZE 0x00038000 // Dest burst size
#define DMAC_SBSIZE 0x00007000 // Source burst size
#define DMAC_TRANSFER_SIZE 0x00000FFF // Transfer size
#define DMAC_DWIDTH_SHIFT 21
#define DMAC_SWIDTH_SHIFT 18
#define DMAC_DBSIZE_SHIFT 15
#define DMAC_SBSIZE_SHIFT 12
// DMAC channel config register
//ZQ add
#define DMAC_DestWMark 0x00600000 //Destination watermark
#define DMAC_SrcWMark 0x00180000 // Source watermark
#define DMAC_CHCONFIG_H 0x00040000 // Halt transfer
#define DMAC_CHCONFIG_A 0x00020000 // Channel is active
#define DMAC_CHCONFIG_L 0x00010000 // Lock transfer
#define DMAC_CHCONFIG_ITC 0x00008000 // Terminal count interrupt enable
#define DMAC_CHCONFIG_IE 0x00004000 // Error interrupt enable
#define DMAC_CHCONFIG_FLOW 0x00003800 // Flow control
#define DMAC_CHCONFIG_DPER 0x000003C0 // Destination peripheral
#define DMAC_CHCONFIG_SPER 0x0000001E // Source peripheral
#define DMAC_CHCONFIG_E 0x00000001 // Channel enable
#define DMAC_FLOW_SHIFT 11
#define DMAC_DPER_SHIFT 6
#define DMAC_SPER_SHIFT 1
// DMAC interrupt status bit definitions
#define DMAC_CHANNEL_0_INT 0x01
#define DMAC_CHANNEL_1_INT 0x02
#define DMAC_CHANNEL_2_INT 0x04
#define DMAC_CHANNEL_3_INT 0x08
#define DMAC_CHANNEL_4_INT 0x10
#define DMAC_CHANNEL_5_INT 0x20
#define DMAC_CHANNEL_6_INT 0x40
#define DMAC_CHANNEL_7_INT 0x80
// DMAC Channel numbers for dynamically allocated SYSINTRs
#define DMAC_CHANNEL_0 ((UCHAR)0x0)
#define DMAC_CHANNEL_1 ((UCHAR)0x1)
#define DMAC_CHANNEL_2 ((UCHAR)0x2)
#define DMAC_CHANNEL_3 ((UCHAR)0x3)
#define DMAC_CHANNEL_4 ((UCHAR)0x4)
#define DMAC_CHANNEL_5 ((UCHAR)0x5)
#define DMAC_CHANNEL_6 ((UCHAR)0x6)
#define DMAC_CHANNEL_7 ((UCHAR)0x7)
// Function prototypes
#ifdef __cplusplus
extern "C" {
#endif
extern BOOL InitDMA(void);
extern BOOL AllocateDMAChannel(PALLOCATE_DMA_PARAMS pParams, PALLOCATE_DMA_RESULT pResults);
extern BOOL InitializeDMAChannel(PINITIALIZE_DMA_PARAMS pParams, PINITIALIZE_DMA_RESULT pResults);
extern BOOL FreeDMAChannel(PFREE_DMA_PARAMS pParams, PFREE_DMA_RESULT pResults);
extern BOOL StartDMATransfer(PSTART_DMA_PARAMS pParams, PSTART_DMA_RESULT pResults);
extern BOOL HaltDMATransfer(PHALT_DMA_PARAMS pParams, PHALT_DMA_RESULT pResults);
extern BOOL RestartDMATransfer(PRESTART_DMA_PARAMS pParams, PRESTART_DMA_RESULT pResults);
extern BOOL StopDMATransfer(PSTOP_DMA_PARAMS pParams, PSTOP_DMA_RESULT pResults);
extern BOOL GetErrorStatus(PGET_ERROR_PARAMS pParams, PGET_ERROR_RESULT pResults);
extern BOOL ClearErrorStatus(PCLEAR_ERROR_PARAMS pParams, PCLEAR_ERROR_RESULT pResults);
extern BOOL GetTCStatus(PGET_TC_PARAMS pParams, PGET_TC_RESULT pResults);
extern BOOL ClearTCStatus(PCLEAR_TC_PARAMS pParams, PCLEAR_TC_RESULT pResults);
extern BOOL GetSysIntrMappings(DMA_GLOB_SYSINTR * pdwSysIntr, UCHAR ucDMAChannel);
extern BOOL GetActiveDmaChannel(DWORD * pdwSysIntr, DWORD * pdwActiveChannel);
extern BOOL FreeDmaSysIntr(PFREE_DMA_SYSINTR_PARAMS pParams, PFREE_DMA_SYSINTR_RESULT pResults );
#ifdef __cplusplus
}
#endif
void AddLLIEntry(UCHAR ucDMAChannel, DWORD dwPage, PDWORD pdwSourceBuffer,
PDWORD pdwDestBuffer, DWORD dwTransferSize);
#endif
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