mpmc.inc

ARM9基于WINDOWSCE的BSP源代码

;/* Bits for Dynamic RAS CAS Latency Register (MPMCDynamicRasCas) */

MPMCDynamicRasCas_RAS_MASK          EQU     0x000F       ;/* 0..3: 0 is reserved, 3 on nPOR, N = number of cycles*/
MPMCDynamicRasCas_CAS_MASK          EQU     0x0780       ;/* 7..10: 0 is reserved, MPMCDYCS5CASDLY on nPOR, N = number of cycles * 2 */

MPMCDynamicRasCas_RAS_1Cycle        EQU     0x0001       ;/* RAS latency of 1 clock cycle  */
MPMCDynamicRasCas_RAS_2Cycles       EQU     0x0002       ;/* RAS latency of 2 clock cycles */
MPMCDynamicRasCas_RAS_3Cycles       EQU     0x0003       ;/* RAS latency of 3 clock cycles */
                                                         ;/* RAS 1..15 are valid */
                                                         
MPMCDynamicRasCas_CAS_0_5_Cycles    EQU     0x0080  ;/* CAS latency of  0.5 clock cycles*/
MPMCDynamicRasCas_CAS_1_0_Cycles    EQU     0x0100  ;/* CAS latency of  1   clock cycles*/
MPMCDynamicRasCas_CAS_1_5_Cycles    EQU     0x0180  ;/* CAS latency of  1.5 clock cycles*/
MPMCDynamicRasCas_CAS_2_0_Cycles    EQU     0x0200  ;/* CAS latency of  2   clock cycles*/
MPMCDynamicRasCas_CAS_2_5_Cycles    EQU     0x0280  ;/* CAS latency of  2.5 clock cycles*/
MPMCDynamicRasCas_CAS_3_0_Cycles    EQU     0x0300  ;/* CAS latency of  3   clock cycles*/
MPMCDynamicRasCas_CAS_3_5_Cycles    EQU     0x0380  ;/* CAS latency of  3.5 clock cycles*/
MPMCDynamicRasCas_CAS_4_0_Cycles    EQU     0x0400  ;/* CAS latency of  4   clock cycles*/
MPMCDynamicRasCas_CAS_4_5_Cycles    EQU     0x0480  ;/* CAS latency of  4.5 clock cycles*/
MPMCDynamicRasCas_CAS_5_0_Cycles    EQU     0x0500  ;/* CAS latency of  5   clock cycles*/
MPMCDynamicRasCas_CAS_5_5_Cycles    EQU     0x0580  ;/* CAS latency of  5.5 clock cycles*/
MPMCDynamicRasCas_CAS_6_0_Cycles    EQU     0x0600  ;/* CAS latency of  6   clock cycles*/
MPMCDynamicRasCas_CAS_6_5_Cycles    EQU     0x0680  ;/* CAS latency of  6.5 clock cycles*/
MPMCDynamicRasCas_CAS_7_0_Cycles    EQU     0x0700  ;/* CAS latency of  7   clock cycles*/
MPMCDynamicRasCas_CAS_7_5_Cycles    EQU     0x0780  ;/* CAS latency of  7.5 clock cycles    Reset Value on nPOR */


;/* Bits for Static Configuration Registers 0 - 3 (MPMCStaticControl[0,1,2,3]) */

MPMCStaticConfig_MW_8Bit            EQU     0x0         ;/* 0..1:Set static memory to 8-bit     */
MPMCStaticConfig_MW_16Bit           EQU     0x1         ;/* 0..1:Set static memory to 16-bit    */
MPMCStaticConfig_MW_32Bit           EQU     0x2         ;/* 0..1:Set static memory to 32-bit    */

MPMCStaticConfig_PM_AsyncDisable    EQU     0x0         ;/* 3: Disable asynchronous page mode */
MPMCStaticConfig_PM_AsyncEnable     EQU     0x8         ;/* 3: Enable asynchronous page mode  */
                                                        ;/* 4..5: reserved */                               
MPMCStaticConfig_PC_High            EQU     0x40        ;/* 6: Active chip select high        */
MPMCStaticConfig_PC_Low             EQU     0x00        ;/* 6: Active chip select low         */

MPMCStaticConfig_PB_High            EQU     0x80        ;/* 7: Byte lane state high           */
MPMCStaticConfig_PB_Low             EQU     0x00        ;/* 7: Byte lane state low            */

MPMCStaticConfig_EW_Disable         EQU     0x000       ;/* 8:Extended wait disabled         */
MPMCStaticConfig_EW_Enable          EQU     0x100       ;/* 8:Extended wait enabled          */

MPMCStaticConfig_P_WriteProtect     EQU     0x100000    ;/* 20: Write protected                */
MPMCStaticConfig_P_WriteNotProtect  EQU     0x000000    ;/* 20: Writes not protected           */


;/*  Bits for AHB Control Registers 0 - 4 (MPMCAHBControl[0,1,2,3,4]) */

MPMCAHBControl_Enable               EQU     0x00001     ;/* Write buffer enabled           */
MPMCAHBControl_Disable              EQU     0x00000     ;/* Write buffer disabled          */


;/* Bits for AHB Status Rgisters 0-4 (MPMPCAHBStatus[0,1,2,3,4]) */

MPMCAHBStatus_Occupied              EQU     0x00002     ;/* Write buffer has data          */
MPMCAHBStatus_Empty                 EQU     0x00000     ;/* Write buffer empty            */



;/* Peripheral and Primecell Identification registers */

;/* First Peripheral ID register group [0..3] */

;/* GX175 Values */
MPMCPeriphID0_Mask                  EQU     0xFF    ;/* non-reserved register area bit mask */
MPMCPeriphID0PartNumber0            EQU     0x75    ;/*    Part Number  :Low Byte   */


;/* GX175 ID1 specific */
MPMCPeriphID1_Mask                  EQU     0xFF    ;/* non-reserved register area bit mask */

MPMCPeriphID1PartNumber1            EQU     0x01    ;/*    Part Number  :High Byte  */
MPMCPeriphID1PartNumber1_Mask       EQU     0x0F    ;/* [00:03] */

MPMCPeriphID1Designer0              EQU     0x10    ;/*    Designer0: Low Nibble: 1 For ARM         */
MPMCPeriphID1Designer0_Mask         EQU     0xF0    ;/* [04:07] */


;/* GX175 ID2 specific */
MPMCPeriphID2_Mask                  EQU     0xFF    ;/* non-reserved register area bit mask */

MPMCPeriphID2Designer1              EQU     0x04    ;/*    Designer0:High Nibble: 4 For ARM         */
MPMCPeriphID2Designer1_Mask         EQU     0x0F    ;/* [00:03] */

MPMCPeriphID2Revision               EQU     0x00    ;/*    Revision: CURRENT REVISION, Treat as minimum */
MPMCPeriphID2Revision_Mask          EQU     0xF0    ;/* [04:07] */


;/* GX175 ID3 specific */
MPMCPeriphID3_Mask                  EQU     0x7F    ;/* non-reserved register area bit mask */

MPMCPeriphID3MBXPort                EQU     0x40    ;/* Indicates MBX Interface Port available*/
MPMCPeriphID3MBXPort_Mask           EQU     0x40    ;/* [06] */

MPMCPeriphID3ConfigAHB              EQU     0x00    ;/* Indicates AHB Bus master Width - 0 = 32bit for GX175 */
MPMCPeriphID3ConfigAHB_Mask         EQU     0x38    ;/* [05:03] */

MPMCPeriphID3ConfigTIC              EQU     0x04    ;/* GX175 specific - 1 = TIC available for GX175 */
MPMCPeriphID3ConfigTIC_Mask         EQU     0x04    ;/* [02]    */

MPMCPeriphID3ConfigDataBuf          EQU     0x02    ;/* GX175 specific - 1 = Data Buffers available for GX175 */
MPMCPeriphID3ConfigDataBuf_Mask     EQU     0x02    ;/* [01]    */

MPMCPeriphID3ConfigSMC              EQU     0x01    ;/* GX175 specific - 1 = SMC Memory controller available for GX175 */
MPMCPeriphID3ConfigSMC_Mask         EQU     0x01    ;/* [00]    */



;/* Second Peripheral ID register group [4..7] */

;/* GX175 Values */
MPMCPeriphID4Config                 EQU     0x05    ;/*    Configuration    : Peripheral specific */
                                                    ;/* 0101= 6 Memory Ports (for GX175) */
MPMCPeriphID4Config_Mask            EQU     0x0F    ;/* [00:07] */

;/* ID 5..7 are reserved */
MPMCPeriphID5VAL                    EQU     0x00    
MPMCPeriphID6VAL                    EQU     0x00     
MPMCPeriphID7VAL                    EQU     0x00    
 

;/* PrimeCell ID Group */
;/* Address offset */
MPMCPCellID0                        EQU     0x0FF0  ;/*Bits 07:00    */
MPMCPCellID1                        EQU     0x0FF4  ;/*Bits 15:08   */
MPMCPCellID2                        EQU     0x0FF8  ;/*Bits 23:16  */
MPMCPCellID3                        EQU     0x0FFC  ;/*Bits 31:24  */

;/* GX175 Values */
MPMCPCellID0VAL                     EQU     0x0D     
MPMCPCellID1VAL                     EQU     0xF0    
MPMCPCellID2VAL                     EQU     0x05     
MPMCPCellID3VAL                     EQU     0xB1     

    ENDIF ; mpmc_inc

    END