mpmc.inc

ARM9基于WINDOWSCE的BSP源代码

;/* Bits for Config Register (MPMCConfig) */

MPMCConfig_N_BigEndian              EQU     0x1     ;/* MPMC is in big-endian mode      */
MPMCConfig_N_LittleEndian           EQU     0x0     ;/* MPMC is in little-endian mode   */


;/* Dynamic memory read config (MPMCDynamicReadConfig) */
                                                        ;/* [01:00] DDR-SDRAM Read Data Stratagy */
MPMCDynamicReadConfig_SRD_OUT           EQU     0x0000  ;/* 00 Clocked out delay, using MPMCCLKOUT */
MPMCDynamicReadConfig_SRD_D0            EQU     0x0001  ;/* 01 Command delayed, using MPMCCLKDELAY (default) */
MPMCDynamicReadConfig_SRD_D1            EQU     0x0002  ;/* 10 Command delayed + 1 Cycle, using MPMCCLKDELAY */
MPMCDynamicReadConfig_SRD_D2            EQU     0x0003  ;/* 11 Command delayed + 2 Cycles, using MPMCCLKDELAY */

MPMCDynamicReadConfig_SRP_PE            EQU     0x0010  ;/* [04] Data read polarity Capture on Positive edge*/
MPMCDynamicReadConfig_SRP_NE            EQU     0x0000  ;/* [04] Data read polarity Capture on Negative edge*/

                                                        ;/* [09:08] DDR-SDRAM Read Data Stratagy */
MPMCDynamicReadConfig_DRD_OUT           EQU     0x0000  ;/* 00 Clocked out delay, using MPMCCLKOUT */
MPMCDynamicReadConfig_DRD_D0            EQU     0x0100  ;/* 01 Command delayed, using MPMCCLKDELAY (default) */
MPMCDynamicReadConfig_DRD_D1            EQU     0x0200  ;/* 10 Command delayed + 1 Cycle, using MPMCCLKDELAY */
MPMCDynamicReadConfig_DRD_D2            EQU     0x0300  ;/* 11 Command delayed + 2 Cycles, using MPMCCLKDELAY */

MPMCDynamicReadConfig_DRP_PE            EQU     0x1000  ;/* [12] Data read polarity Capture on Positive edge (default)*/
MPMCDynamicReadConfig_DRP_NE            EQU     0x0000  ;/* [12] Data read polarity Capture on Negative edge*/


;/* Bits for Dynamic Control Register (MPMCDynamicControl) */

MPMCDynamicControl_CE_Enable            EQU     0x01    ;/* 0:All clock enables are driven high continuously        */
MPMCDynamicControl_CE_Disable           EQU     0x00    ;/* 0:Clock enable of idle devices deasserted to save power */

MPMCDynamicControl_CS_Continuous        EQU     0x02    ;/* 1:CLKOUT runs continuously          */
MPMCDynamicControl_CS_Stop              EQU     0x00    ;/* 1:CLKOUT stops when SDRAMS are idle */

MPMCDynamicControl_SR_SelfRefresh       EQU     0x04    ;/* 2:Enter self-refresh mode */
MPMCDynamicControl_SR_Normal            EQU     0x00    ;/* 2:Normal mode             */

MPMCDynamicControl_SR_MCC_cont          EQU     0x00    ;/* 3:MPMCCLKOUT and nMPMCCLKOUT continuous   */
MPMCDynamicControl_SR_MCC_stop          EQU     0x08    ;/* 3:MPMCCLKOUT and nMPMCCLKOUT stop during self refresh   */

MPMCDynamicControl_MCC_DDR_Enable       EQU     0x00    ;/* 4:nMPMCCLKOUT enable */
MPMCDynamicControl_MCC_DDR_Disable      EQU     0x10    ;/* 4:nMPMCCLKOUT disable (if no DDR-SDRAM transactions) */

MPMCDynamicControl_MCC_SDR_Enable       EQU     0x00    ;/* 5:MPMCCLKOUT enable */
MPMCDynamicControl_MCC_SDR_Disable      EQU     0x20    ;/* 5:MPMCCLKOUT disable (if no SDRAM transactions) */
                                                        ;/* 6:Reserved */
MPMCDynamicControl_I_SDRAMNOP           EQU     0x180   ;/* 8..7:Issue no operation command     */
MPMCDynamicControl_I_SDRAMPALL          EQU     0x100   ;/* 8..7:Issue pre-charge command       */
MPMCDynamicControl_I_SDRAMMODE          EQU     0x080   ;/* 8..7:Issue mode command             */
MPMCDynamicControl_I_SDRAMNORMAL        EQU     0x000   ;/* 8..7:Issue normal operation command */

MPMCDynamicControl_DLL_DS_Enable        EQU     0x200   ;/* 09:DLL Calibrating              :Indicates the value of MPMCDLLCALIBREQ for software control of DLL Hand shaking */
MPMCDynamicControl_DLL_DS_Disable       EQU     0x000   ;/* 09:DLL Calibration complete     :Indicates the value of MPMCDLLCALIBREQ for software control of DLL Hand shaking */

MPMCDynamicControl_DLL_DC_Enable        EQU     0x400   ;/* 10:Enable software control of DLL Hand shaking MPMCDLLCALIBREQ for initial DLL calibration */
MPMCDynamicControl_DLL_DC_Disable       EQU     0x000   ;/* 10:Disable */

MPMCDynamicControl_DLL_DE_Enable        EQU     0x800   ;/* 11:Enable DLL Handshaking MPMCDLLCALIBREQ during auto-refresh cycles */
MPMCDynamicControl_DLL_DE_Disable       EQU     0x000   ;/* 11:Disable */
                                                        ;/* 12:Reserved */                                                  
MPMCDynamicControl_DP_PowerDown         EQU     0x2000  ;/* 13:Enter deep power down mode */
MPMCDynamicControl_DP_PowerNormal       EQU     0x0000  ;/* 13:Normal operation           */

MPMCDynamicControl_nRP_High             EQU     0x4000  ;/* 14:Set nMPMCRPOUT signal high */
MPMCDynamicControl_nRP_Low              EQU     0x0000  ;/* 14:Set nMPMCRPOUT signal low  */

MPMCDynamicControl_MPMCRPVHHOUT_High    EQU     0x8000  ;/* 15:Set nMPMCRPVHHOUT high voltage   */
MPMCDynamicControl_MPMCRPVHHOUT_Normal  EQU     0x0000  ;/* 15:Set nMPMCRPVHHOUT normal voltage */


;/* Bits for Dynamic Configuration [0,1,2,3] Register (MPMCDynamicConfig) */

MPMCDynamicConfig_AM_32bit_4Mx16        EQU     0x4280      ;/* High performance address mapping for a 32 bit 4M X 16 SDRAM (64Meg) */

;/* Bits [14:07] */
                                                                                    
;/* 16-bit  external    bus external    high-performance    address mapping (Row,   Bank,   Column) */                                      
MPMCDynamicConfig_AM_16HI_2Mx8          EQU     0x0000  ;/* 0x00    0   0   0   0   16MB    (2Mx8),     2   banks,  row length  =   11, column  length  =   9   */
MPMCDynamicConfig_AM_16HI_1Mx16         EQU     0x0080  ;/* 0x01    0   0   0   1   16MB    (1Mx16),    2   banks,  row length  =   11, column  length  =   8   */
MPMCDynamicConfig_AM_16HI_8Mx8          EQU     0x0200  ;/* 0x04    0   0   1   0   64MB    (8Mx8),     4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_16HI_4Mx16         EQU     0x0280  ;/* 0x05    0   0   1   1   64MB    (4Mx16),    4   banks,  row length  =   12, column  length  =   8   */
MPMCDynamicConfig_AM_16HI_16Mx8         EQU     0x0400  ;/* 0x08    0   0   10  0   128MB   (16Mx8),    4   banks,  row length  =   12, column  length  =   10  */
MPMCDynamicConfig_AM_16HI_8Mx16         EQU     0x0480  ;/* 0x09    0   0   10  1   128MB   (8Mx16),    4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_16HI_32Mx8         EQU     0x0600  ;/* 0x0C    0   0   11  0   256MB   (32Mx8),    4   banks,  row length  =   13, column  length  =   10  */
MPMCDynamicConfig_AM_16HI_16Mx16        EQU     0x0680  ;/* 0x0D    0   0   11  1   256MB   (16Mx16),   4   banks,  row length  =   13, column  length  =   9   */
MPMCDynamicConfig_AM_16HI_64Mx8         EQU     0x0800  ;/* 0x10    0   0   100 0   512MB   (64Mx8),    4   banks,  row length  =   13, column  length  =   11  */
MPMCDynamicConfig_AM_16HI_32Mx16        EQU     0x0880  ;/* 0x11    0   0   100 1   512MB   (32Mx16),   4   banks,  row length  =   13, column  length  =   10  */

;/* 16-bit  0x0000  bus external    Low-power   SDRAM   address mapping (Bank,  Row,    Column) */                                  
MPMCDynamicConfig_AM_16LO_2Mx8          EQU     0x1000  ;/* 0x20    0   1   0   0   16MB    (2Mx8),     2   banks,  row length  =   11, column  length  =   9   */
MPMCDynamicConfig_AM_16LO_1Mx16         EQU     0x1080  ;/* 0x21    0   1   0   1   16MB    (1Mx16),    2   banks,  row length  =   11, column  length  =   8   */
MPMCDynamicConfig_AM_16LO_8Mx8          EQU     0x1200  ;/* 0x24    0   1   1   0   64MB    (8Mx8),     4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_16LO_4Mx16         EQU     0x1280  ;/* 0x25    0   1   1   1   64MB    (4Mx16),    4   banks,  row length  =   12, column  length  =   8   */
MPMCDynamicConfig_AM_16LO_16Mx8         EQU     0x1400  ;/* 0x28    0   1   10  0   128MB   (16Mx8),    4   banks,  row length  =   12, column  length  =   10  */
MPMCDynamicConfig_AM_16LO_8Mx16         EQU     0x1480  ;/* 0x29    0   1   10  1   128MB   (8Mx16),    4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_16LO_32Mx8         EQU     0x1600  ;/* 0x2C    0   1   11  0   256MB   (32Mx8),    4   banks,  row length  =   13, column  length  =   10  */
MPMCDynamicConfig_AM_16LO_16Mx16        EQU     0x1680  ;/* 0x2D    0   1   11  1   256MB   (16Mx16),   4   banks,  row length  =   13, column  length  =   9   */
MPMCDynamicConfig_AM_16LO_64Mx8         EQU     0x1800  ;/* 0x30    0   1   100 0   512MB   (64Mx8),    4   banks,  row length  =   13, column  length  =   11  */
MPMCDynamicConfig_AM_16LO_32Mx16        EQU     0x1880  ;/* 0x31    0   1   100 1   512MB   (32Mx16),   4   banks,  row length  =   13, column  length  =   10  */

;/* 32-bit  0x0000  bus external    High    performance address mapping (Row,   Bank,   Column) */                                  
MPMCDynamicConfig_AM_32HI_2Mx8          EQU     0x4000  ;/* 0x80    1   0   0   0   16MB    (2Mx8),     2   banks,  row length  =   11, column  length  =   9   */
MPMCDynamicConfig_AM_32HI_1Mx16         EQU     0x4080  ;/* 0x81    1   0   0   1   16MB    (1Mx16),    2   banks,  row length  =   11, column  length  =   8   */
MPMCDynamicConfig_AM_32HI_8Mx8          EQU     0x4200  ;/* 0x84    1   0   1   0   64MB    (8Mx8),     4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_32HI_4Mx16         EQU     0x4280  ;/* 0x85    1   0   1   1   64MB    (4Mx16),    4   banks,  row length  =   12, column  length  =   8   */
MPMCDynamicConfig_AM_32HI_2Mx32         EQU     0x4300  ;/* 0x86    1   0   1   10  64MB    (2Mx32),    4   banks,  row length  =   11, column  length  =   8   */
MPMCDynamicConfig_AM_32HI_16Mx8         EQU     0x4400  ;/* 0x88    1   0   10  0   128MB   (16Mx8),    4   banks,  row length  =   12, column  length  =   10  */
MPMCDynamicConfig_AM_32HI_8Mx16         EQU     0x4480  ;/* 0x89    1   0   10  1   128MB   (8Mx16),    4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_32HI_4Mx32         EQU     0x4500  ;/* 0x8A    1   0   10  10  128MB   (4Mx32),    4   banks,  row length  =   12, column  length  =   8   */
MPMCDynamicConfig_AM_32HI_32Mx8         EQU     0x4600  ;/* 0x8C    1   0   11  0   256MB   (32Mx8),    4   banks,  row length  =   13, column  length  =   10  */
MPMCDynamicConfig_AM_32HI_16Mx16        EQU     0x4680  ;/* 0x8D    1   0   11  1   256MB   (16Mx16),   4   banks,  row length  =   13, column  length  =   9   */
MPMCDynamicConfig_AM_32HI_8Mx32         EQU     0x4700  ;/* 0x8E    1   0   11  10  256MB   (8Mx32),    4   banks,  row length  =   13, column  length  =   8   */
MPMCDynamicConfig_AM_32HI_64Mx8         EQU     0x4800  ;/* 0x90    1   0   100 0   512MB   (64Mx8),    4   banks,  row length  =   13, column  length  =   11  */
MPMCDynamicConfig_AM_32HI_32Mx16        EQU     0x4880  ;/* 0x91    1   0   100 1   512MB   (32Mx16),   4   banks,  row length  =   13, column  length  =   10  */

;/* 32-bit  0x0000  bus external    Low-power   SDRAM   address mapping (Bank,  Row,    Column) */                                  
MPMCDynamicConfig_AM_32LO_2Mx8          EQU     0x5000  ;/* 0xA0    1   1   0   0   16MB    (2Mx8),     2   banks,  row length  =   11, column  length  =   9   */
MPMCDynamicConfig_AM_32LO_1Mx16         EQU     0x5080  ;/* 0xA1    1   1   0   1   16MB    (1Mx16),    2   banks,  row length  =   11, column  length  =   8   */
MPMCDynamicConfig_AM_32LO_8Mx8          EQU     0x5200  ;/* 0xA4    1   1   1   0   64MB    (8Mx8),     4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_32LO_4Mx16         EQU     0x5280  ;/* 0xA5    1   1   1   1   64MB    (4Mx16),    4   banks,  row length  =   12, column  length  =   8   */
MPMCDynamicConfig_AM_32LO_2Mx32         EQU     0x5300  ;/* 0xA6    1   1   1   10  64MB    (2Mx32),    4   banks,  row length  =   11, column  length  =   8   */
MPMCDynamicConfig_AM_32LO_16Mx8         EQU     0x5400  ;/* 0xA8    1   1   10  0   128MB   (16Mx8),    4   banks,  row length  =   12, column  length  =   10  */
MPMCDynamicConfig_AM_32LO_8Mx16         EQU     0x5480  ;/* 0xA9    1   1   10  1   128MB   (8Mx16),    4   banks,  row length  =   12, column  length  =   9   */
MPMCDynamicConfig_AM_32LO_4Mx32         EQU     0x5500  ;/* 0xAA    1   1   10  10  128MB   (4Mx32),    4   banks,  row length  =   12, column  length  =   8   */
MPMCDynamicConfig_AM_32LO_32Mx8         EQU     0x5600  ;/* 0xAC    1   1   11  0   256MB   (32Mx8),    4   banks,  row length  =   13, column  length  =   10  */
MPMCDynamicConfig_AM_32LO_16Mx16        EQU     0x5680  ;/* 0xAD    1   1   11  1   256MB   (16Mx16),   4   banks,  row length  =   13, column  length  =   9   */
MPMCDynamicConfig_AM_32LO_8Mx32         EQU     0x5700  ;/* 0xAE    1   1   11  10  256MB   (8Mx32),    4   banks,  row length  =   13, column  length  =   8   */
MPMCDynamicConfig_AM_32LO_64Mx8         EQU     0x5800  ;/* 0xB0    1   1   100 0   512MB   (64Mx8),    4   banks,  row length  =   13, column  length  =   11  */
MPMCDynamicConfig_AM_32LO_32Mx16        EQU     0x5880  ;/* 0xB1    1   1   100 1   512MB   (32Mx16),   4   banks,  row length  =   13, column  length  =   10  */



MPMCDynamicConfig_P_WriteProtect    EQU     0x100000    ;/* Write protected      */
MPMCDynamicConfig_P_WriteNotProtect EQU     0x000000    ;/* Writes not protected */

MPMCDynamicConfig_MD_SDR            EQU     0x00        ;/* 000 Normal SDRAM reset on nPOR */
MPMCDynamicConfig_MD_SDR_MS_FLASH   EQU     0x01        ;/* 001 SDR Micron Sync Flash */
MPMCDynamicConfig_MD_SDR_LP         EQU     0x02        ;/* 010 Low-power SDR SDRAM */
                                                        ;/* 011 reserved */
                                                
MPMCDynamicConfig_MD_DDR            EQU     0x04        ;/* 100 DDR-SDRAM */
MPMCDynamicConfig_MD_DDR_MS_FLASH   EQU     0x05        ;/* 101 DDR Micron Sync Flash */
MPMCDynamicConfig_MD_DDR_LP         EQU     0x06        ;/* 110 Low-power DDR SDRAM */
                                                        ;/* 111 reserved */