mpmc.inc

ARM9基于WINDOWSCE的BSP源代码

;   The content of this file or document is CONFIDENTIAL and PROPRIETARY
;   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
;   License Agreement between Licensee and Jade Technologies Co., Ltd.
;   restricting among other things, the use, reproduction, distribution
;   and transfer.  Each of the embodiments, including this information 
;   and any derivative work shall retain this copyright notice.
; 
;   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
;   All rights reserved.
; ----------------------------------------------------------------
;  File:     mpmc.inc,v
;  Revision: 1.0
; ----------------------------------------------------------------
;  $
; 

 IF :LNOT: :DEF: mpmc_inc
mpmc_inc        EQU     1

;/*
; * This file is for Multi-Port Memory controller (MPMC) initialization
; */

;/*
; * MPMC Register Offsets  - GX175
; */
MPMCControl                         EQU     0x00    ;/* Control register                                                                    */
MPMCStatus                          EQU     0x04    ;/* Status register                                                                     */
MPMCConfig                          EQU     0x08    ;/* Configuration register                                                              */
MPMCDynamicControl                  EQU     0x20    ;/* Dynamic memory control register                                                     */
MPMCDynamicRefresh                  EQU     0x24    ;/* Dynamic memory refresh timer                                                        */
MPMCDynamicReadConfig               EQU     0x28    ;/* Dynamic memory read config                                                          */
MPMCDynamictRP                      EQU     0x30    ;/* Dynamic memory precharge comand period                                              */
MPMCDynamictRAS                     EQU     0x34    ;/* Dynamic memory active to precharge command period (tRAS)                            */
MPMCDynamictSREX                    EQU     0x38    ;/* Dynamic memory self-refresh exit time (tSREX)                                       */

MPMCDynamictWR                      EQU     0x44    ;/* Dynamic memory write recovery time (tWR)                                            */
MPMCDynamictRC                      EQU     0x48    ;/* Dynamic memory active to active command period (tRC)                                */
MPMCDynamictRFC                     EQU     0x4C    ;/* Dynamic memory auto refresh period and auto refresh to active command period (tRFC) */
MPMCDynamictXSR                     EQU     0x50    ;/* Dynamic memory exit self-refresh to active command time (tXSR)                      */
MPMCDynamictRRD                     EQU     0x54    ;/* Dynamic memory active bank A to active B time (tRRD)                                */
MPMCDynamictMRD                     EQU     0x58    ;/* Dynamic memory load mode register to active command time (tMRD)                     */

MPMCDynamicCLDR                     EQU     0x5C    ;/* Dyanmic Memory last data in to read command time

MPMCStaticExtendedWait              EQU     0x80    ;/* Static memory extended wait */

MPMCDynamicConfig0                  EQU     0x100   ;/* Dynamic memory configuration register */
MPMCDynamicRasCas0                  EQU     0x104   ;/* Dynamic memory RAS and CAS delay      */
MPMCDynamicConfig1                  EQU     0x120   ;/* Dynamic memory configuration register */
MPMCDynamicRasCas1                  EQU     0x124   ;/* Dynamic memory RAS and CAS delay      */
MPMCDynamicConfig2                  EQU     0x140   ;/* Dynamic memory configuration register */
MPMCDynamicRasCas2                  EQU     0x144   ;/* Dynamic memory RAS and CAS delay      */
MPMCDynamicConfig3                  EQU     0x160   ;/* Dynamic memory configuration register */
MPMCDynamicRasCas3                  EQU     0x164   ;/* Dynamic memory RAS and CAS delay      */

MPMCStaticConfig0                   EQU     0x200   ;/* Static memory configuration register */
MPMCStaticWaitWen0                  EQU     0x204   ;/* Static memory write enable delay     */
MPMCStaticWaitOen0                  EQU     0x208   ;/* Static memory output enable delay    */
MPMCStaticWaitRd0                   EQU     0x20C   ;/* Static memory read delay             */
MPMCStaticWaitPage0                 EQU     0x210   ;/* Static memory page mode read delay   */
MPMCStaticWaitWr0                   EQU     0x214   ;/* Static memory write delay            */
MPMCStaticWaitTurn0                 EQU     0x218   ;/* Static memory turn around delay      */

MPMCStaticConfig1                   EQU     0x220   ;/* Static memory configuration register */
MPMCStaticWaitWen1                  EQU     0x224   ;/* Static memory write enable delay     */
MPMCStaticWaitOen1                  EQU     0x228   ;/* Static memory output enable delay    */
MPMCStaticWaitRd1                   EQU     0x22C   ;/* Static memory read delay             */
MPMCStaticWaitPage1                 EQU     0x230   ;/* Static memory page mode read delay   */
MPMCStaticWaitWr1                   EQU     0x234   ;/* Static memory write delay            */
MPMCStaticWaitTurn1                 EQU     0x238   ;/* Static memory turn around delay      */

MPMCStaticConfig2                   EQU     0x240   ;/* Static memory configuration register */
MPMCStaticWaitWen2                  EQU     0x244   ;/* Static memory write enable delay     */
MPMCStaticWaitOen2                  EQU     0x248   ;/* Static memory output enable delay    */
MPMCStaticWaitRd2                   EQU     0x24C   ;/* Static memory read delay             */
MPMCStaticWaitPage2                 EQU     0x250   ;/* Static memory page mode read delay   */
MPMCStaticWaitWr2                   EQU     0x254   ;/* Static memory write delay            */
MPMCStaticWaitTurn2                 EQU     0x258   ;/* Static memory turn around delay      */

MPMCStaticConfig3                   EQU     0x260   ;/* Static memory configuration register */
MPMCStaticWaitWen3                  EQU     0x264   ;/* Static memory write enable delay     */
MPMCStaticWaitOen3                  EQU     0x268   ;/* Static memory output enable delay    */
MPMCStaticWaitRd3                   EQU     0x26C   ;/* Static memory read delay             */
MPMCStaticWaitPage3                 EQU     0x270   ;/* Static memory page mode read delay   */
MPMCStaticWaitWr3                   EQU     0x274   ;/* Static memory write delay            */
MPMCStaticWaitTurn3                 EQU     0x278   ;/* Static memory turn around delay      */


;/* AHB Control registers */

MPMCAHBControl0                     EQU     0x400   ;/* AHB buffer enable */
MPMCAHBStatus0                      EQU     0x404   ;/* AHB status: contents */
MPMCAHBTimeOut0                     EQU     0x408   ;/* AHB 10 Bit Service Timeout register

MPMCAHBControl1                     EQU     0x420   ;/* AHB buffer enable */
MPMCAHBStatus1                      EQU     0x424   ;/* AHB status: contents */
MPMCAHBTimeOut1                     EQU     0x428   ;/* AHB 10 Bit Service Timeout register

MPMCAHBControl2                     EQU     0x440   ;/* AHB buffer enable */
MPMCAHBStatus2                      EQU     0x444   ;/* AHB status: contents */
MPMCAHBTimeOut2                     EQU     0x448   ;/* AHB 10 Bit Service Timeout register

MPMCAHBControl3                     EQU     0x460   ;/* AHB buffer enable */
MPMCAHBStatus3                      EQU     0x464   ;/* AHB status: contents */
MPMCAHBTimeOut3                     EQU     0x468   ;/* AHB 10 Bit Service Timeout register

MPMCAHBControl4                     EQU     0x480   ;/* AHB buffer enable */
MPMCAHBStatus4                      EQU     0x484   ;/* AHB status: contents */
MPMCAHBTimeOut4                     EQU     0x488   ;/* AHB 10 Bit Service Timeout register


;/* First Peripheral ID register group [0..3] */
MPMCPeriphID0                       EQU     0x0FE0  ;/*Bits 07:00   */
MPMCPeriphID1                       EQU     0x0FE4  ;/*Bits 15:08  */
MPMCPeriphID2                       EQU     0x0FE8  ;/*Bits 23:16 */
MPMCPeriphID3                       EQU     0x0FEC  ;/*Bits 31:24 */

;/* Second Peripheral ID register group [4..7] */
MPMCPeriphID4                       EQU     0x0FD0  ;/*Bits 07:00  */
MPMCPeriphID5                       EQU     0x0FD4  ;/*Bits 15:08  */
MPMCPeriphID6                       EQU     0x0FD8  ;/*Bits 23:16  */
MPMCPeriphID7                       EQU     0x0FDC  ;/*Bits 31:24  */
 
 
;/* Data Definitions and masks for above registers */
;----------------------------------------------------
  
;/* Bits for Control Register (MPMCControl) */
        
MPMCControl_E_Enable                EQU     0x01    ;/* Enable MPMC  */
MPMCControl_E_Disable               EQU     0x00    ;/* Disable MPMC */

MPMCControl_L_LowPower              EQU     0x04    ;/* Low-power mode    */
MPMCControl_L_NormalPower           EQU     0x00    ;/* Normal power mode */


;/* Bits for Status Register (MPMCStatus) */

MPMCStatus_B_Busy                   EQU     0x01    ;/* MPMC is busy                    */
MPMCStatus_B_Idle                   EQU     0x00    ;/* MPMC is idle                    */
                
MPMCStatus_SA_SelfRefreshMode       EQU     0x04    ;/* MPMC is in self-refresh mode    */
MPMCStatus_SA_NormalMode            EQU     0x00    ;/* MPMC is in normal mode          */