📄 cpumodes.inc
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;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
; -*-Asm-*-
;
; $Revision: 1.0 $
; $File$
;
; - Defines for processor status register on ARM architectures
;
; $Copyright:
; ----------------------------------------------------------------
; The content of this file or document is CONFIDENTIAL and PROPRIETARY
; to Jade Technologies Co., Ltd. It is subjected to the terms of a
; License Agreement between Licensee and Jade Technologies Co., Ltd.
; restricting among other things, the use, reproduction, distribution
; and transfer. Each of the embodiments, including this information
; and any derivative work shall retain this copyright notice.
;
; Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
; All rights reserved.
; ----------------------------------------------------------------
; File: cpumodes.inc,v
; Revision: 1.0
; ----------------------------------------------------------------
; $
;
IF :LNOT: :DEF: cpumodes_inc
cpumodes_inc EQU 1
; CPSR bits
NoIRQ EQU BIT7 ;
NoFIQ EQU BIT6
NoINTS EQU (NoIRQ | NoFIQ) ; Both
MaskINTS EQU NoINTS
ModeMask EQU 0x1F ; /* Processor mode in CPSR */
SVC32Mode EQU 0x13
IRQ32Mode EQU 0x12
FIQ32Mode EQU 0x11
User32Mode EQU 0x10
;; /* Error modes */
Abort32Mode EQU 0x17
Undef32Mode EQU 0x1B
ENDIF ; cpumodes_inc
END ; End of file
; EOF cpumodes.s
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