mmumacro.inc

ARM9基于WINDOWSCE的BSP源代码

;   The content of this file or document is CONFIDENTIAL and PROPRIETARY
;   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
;   License Agreement between Licensee and Jade Technologies Co., Ltd.
;   restricting among other things, the use, reproduction, distribution
;   and transfer.  Each of the embodiments, including this information 
;   and any derivative work shall retain this copyright notice.
; 
;   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
;   All rights reserved.
; ----------------------------------------------------------------
; File:     mmumacro.inc,v
; Revision: 1.0
; ----------------------------------------------------------------
; $
;
; -*-Asm-*-
;
;    - This file contains the COPROCESSOR access macros for the
;             ARM processors
;

 IF :LNOT: :DEF: mmumacro_inc
mmumacro_inc        EQU     1

;------------------------------------------------------------------
;Read CPU Code (ID, Vendor revision etc.) register 
;
    MACRO
    RDCPU_CODE  $id
    MRC p15, 0, $id, c0, c0 ,0
    MEND

;Extract CPU ID from CPU Code register
;
    MACRO
    RDCPU_ID    $id, $tmp
    MRC p15, 0, $id, c0, c0 ,0
    MOV $tmp, $id, LSL #16  ; Clear bits 16-31
    MOV $tmp, $tmp, LSR #20 ; Move bits 15-3 to 12-0
    MEND

;Extract Revision from CPU Code register
;
    MACRO
    RDCPU_REV   $id, $tmp
    MRC p15, 0, $id, c0, c0 ,0
    MOV $tmp, $id, LSL #28  ; Clear bits 4-31
    MOV $tmp, $tmp, LSR #28 ; Move bits 3-0 back again
    MEND

;Extract CPU Vendor from CPU Code register
;
    MACRO
    RDCPU_VENDOR    $id, $tmp
    MRC p15, 0, $id, c0, c0 ,0
    MOV $tmp, $id, LSR #24  ; Move bits 31-24 to 7-0
    MEND

;Coprocessor read of ID register (cache line sizes)
;
    MACRO
    RDCACHE_SIZES $reg_number
    MRC p15, 0, $reg_number, c0, c0 ,1
    MEND

;Coprocessor read of Control register 
;
    MACRO
    RDMMU_STATE $reg_number
    MRC p15, 0, $reg_number, c1, c0 ,0
    MEND

;Coprocessor write of Control register 
;
    MACRO 
    WRMMU_STATE $reg_number
    MCR p15, 0, $reg_number, c1, c0 ,0
    MEND

; ------------------------------------------------------------------
;Coprocessor cache control 
;Flush I & D Caches
;
    MACRO 
    WRCACHE_FlushIDC $reg_number
    MCR p15,0,$reg_number,c7,c7,0
    MEND

;Coprocessor cache control 
;Flush ICache
;
    MACRO 
    WRCACHE_FlushIC $reg_number
    MCR p15,0,$reg_number,c7,c5,0
    MEND

;Coprocessor cache control 
;Flush DCache
;
    MACRO 
    WRCACHE_FlushDC $reg_number
    MCR p15,0,$reg_number,c7,c6,0
    MEND

;Coprocessor cache control 
;Flush DCache entry
;
    MACRO 
    WRCACHE_CacheFlushDentry $reg_number
    MCR p15,0,$reg_number,c7,c6,1
    MEND

;Coprocessor cache control 
;Clean DCache entry
;
    MACRO 
    WRCACHE_CleanDCentry $reg_number
    MCR p15,0,$reg_number,c7,c10,1
    MEND

;Coprocessor cache control 
;Clean DCache
;
    MACRO 
    WRCACHE_CleanDCache $w1, $w2, $w3, $w4, $w5, $w6
    RDCACHE_SIZES   $w2     ; Get cache information

    MOV $w3, #7         ; 3 bit mask
    AND $w4, $w3, $w2, LSR #18  ; Get Cache Size
    AND $w5, $w3, $w2, LSR #15  ; Get Cache Associativity
    AND $w6, $w3, $w2, LSR #12  ; Get Base and Line Length
    MOVS    $w3, $w6, LSR #2    ; Get Base (and set flags)
    AND $w6, $w6, #3        ; Get Line Length

    ; Calculate LSB of Index field
    ;
    ; 32 - Cache Associativity - Base
    RSB $w2, $w5, #32
    SUB $w2, $w2, $w3

    ; Calculate MSB of Segment field
    ;
    ; 8 + Cache Size - Cache Associativity
    ADD $w3, $w4, #8
    SUB $w3, $w3, $w5

    ; Calculate LSB of Segment field
    ;
    ; Line Length + 3
    ADD $w4, $w6, #3

    ; Calculate max value for Index field
    RSB $w5, $w2, #32
    MOV $w6, #1
    MOV $w5, $w6, LSL $w5
    SUBNE   $w5, $w5, $w5, LSR #2
    SUB $w5, $w5, #1

    ; Calculate max value for Segment field
    SUB $w3, $w3, $w4
    ADD $w3, $w3, #1
    MOV $w3, $w6, LSL $w3
    SUB $w3, $w3, #1

    ; Now finally clean the cache
1   MOV $w6, $w3
2   MOV $w1, $w5, LSL $w2
    ORR $w1, $w1, $w6, LSL $w4
    MCR p15, 0, $w1, c7, c10, 2 ; Clean Line by Index (Not Address)
    SUBS    $w6, $w6, #1
    BGE %B2
    SUBS    $w5, $w5, #1
    BGE %B1

    MEND

;Coprocessor cache control 
;Clean + Flush DCache entry
;
    MACRO 
    WRCACHE_Clean_FlushDCentry $reg_number
    MCR p15,0,$reg_number,c7,c14,1
    MEND

;Drain Write Buffer.
;
    MACRO
    WRCACHE_DrainWriteBuffer $reg_number
    MCR p15,0,$reg_number,c7,c10,4
    MEND

;Flush TLB 
;
    MACRO
    WRMMU_FlushTB $reg_number
    MCR p15,0,$reg_number,c8,c7,0
    MEND

;Flush Instruction TLB 
;
    MACRO
    WRMMU_FlushITB $reg_number
    MCR p15,0,$reg_number,c8,c5,0
    MEND

;Flush Data TLB
;
    MACRO
    WRMMU_FlushDTB $reg_number
    MCR p15,0,$reg_number,c8,c6,0
    MEND

;Clean DCache (only) from address in $reg1 to (excl) addr in $reg2
;
    MACRO
    CleanDCacheRange $reg1, $reg2
1      
        WRCACHE_CleanDCentry $reg1
        ADD     $reg1, $reg1, #32
        CMP     $reg1, $reg2
        BLT     %B1
    MEND

; ------------------------------------------------------------------
;Coprocessor test/clock/idle control 
;Enable Clock Switching
;
    MACRO
    WRCLK_EnableClockSW $reg
    RDMMU_STATE $reg
    ORR $reg, $reg, #0xC0000000
    WRMMU_STATE $reg
    MEND

;Coprocessor test/clock/idle control 
;Disable Clock Switching
;
    MACRO
    WRCLK_DisableClockSW $reg
    RDMMU_STATE $reg
    BIC $reg, $reg, #0xC0000000
    WRMMU_STATE $reg
    MEND

    ENDIF ; mmumacro_inc

    END

; EOF