📄 ssmc.inc
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; The content of this file or document is CONFIDENTIAL and PROPRIETARY
; to Jade Technologies Co., Ltd. It is subjected to the terms of a
; License Agreement between Licensee and Jade Technologies Co., Ltd.
; restricting among other things, the use, reproduction, distribution
; and transfer. Each of the embodiments, including this information
; and any derivative work shall retain this copyright notice.
;
; Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
; All rights reserved.
; ----------------------------------------------------------------
; File: ssmc.inc,v
; Revision: 1.0
; ----------------------------------------------------------------
; $
;
IF :LNOT: :DEF: ssmc_inc
ssmc_inc EQU 1
;/*
; * This file is for Synchronous Static Memory controller (SSMC) initialization
; */
;/*************************************************************************************/
SSMCPeriphID0 EQU 0xFE0 ;/* Peripheral ID for SSMC */
SSMC_PL093_PID0 EQU 0x93 ;/* SSMC PL093 Identification values */
;/*************************************************************************************/
SSMCRmapClr EQU 0x100 ;/* Flag to clear the Remap functionality */
;/* bit [8] of the System Controller SCCTRL register on SP803 and SP810 */
;/*************************************************************************************/
;/* */
;/* SSMC Register Offsets for Memory Banks 0-7 */
;/* */
;/*************************************************************************************/
;/* SSMC Register Offsets for Memory Bank 0 */
SMBMemBank0 EQU 0x00
SMB093IDCYR0 EQU 0x00 ;/* Idle-cycle control register */
SMB093WStRdR0 EQU 0x04 ;/* Wait state Read control register */
SMB093WStWrR0 EQU 0x08 ;/* Wait state Write control register */
SMB093WSTOENR0 EQU 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR0 EQU 0x10 ;/* Write enable assertion delay control register */
SMB093CR0 EQU 0x14 ;/* Control register */
SMB093SR0 EQU 0x18 ;/* Status register */
SMB093WstBRdR0 EQU 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* SSMC Register Offsets for Memory Bank 1 */
SMBMemBank1 EQU SMBMemBank0 + 0x20
SMB093IDCYR1 EQU SMBMemBank1 + 0x00 ;/* Idle-cycle control register */
SMB093WStRdR1 EQU SMBMemBank1 + 0x04 ;/* Wait state Read control register */
SMB093WStWrR1 EQU SMBMemBank1 + 0x08 ;/* Wait state Write control register */
SMB093WSTOENR1 EQU SMBMemBank1 + 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR1 EQU SMBMemBank1 + 0x10 ;/* Write enable assertion delay control register */
SMB093CR1 EQU SMBMemBank1 + 0x14 ;/* Control register */
SMB093SR1 EQU SMBMemBank1 + 0x18 ;/* Status register */
SMB093WstBRdR1 EQU SMBMemBank1 + 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* SSMC Register Offsets for Memory Bank 2 */
SMBMemBank2 EQU SMBMemBank1 + 0x20
SMB093IDCYR2 EQU SMBMemBank2 + 0x00 ;/* Idle-cycle control register */
SMB093WStRdR2 EQU SMBMemBank2 + 0x04 ;/* Wait state Read control register */
SMB093WStWrR2 EQU SMBMemBank2 + 0x08 ;/* Wait state Write control register */
SMB093WSTOENR2 EQU SMBMemBank2 + 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR2 EQU SMBMemBank2 + 0x10 ;/* Write enable assertion delay control register */
SMB093CR2 EQU SMBMemBank2 + 0x14 ;/* Control register */
SMB093SR2 EQU SMBMemBank2 + 0x18 ;/* Status register */
SMB093WstBRdR2 EQU SMBMemBank2 + 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* SSMC Register Offsets for Memory Bank 3 */
SMBMemBank3 EQU SMBMemBank2 + 0x20
SMB093IDCYR3 EQU SMBMemBank3 + 0x00 ;/* Idle-cycle control register */
SMB093WStRdR3 EQU SMBMemBank3 + 0x04 ;/* Wait state Read control register */
SMB093WStWrR3 EQU SMBMemBank3 + 0x08 ;/* Wait state Write control register */
SMB093WSTOENR3 EQU SMBMemBank3 + 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR3 EQU SMBMemBank3 + 0x10 ;/* Write enable assertion delay control register */
SMB093CR3 EQU SMBMemBank3 + 0x14 ;/* Control register */
SMB093SR3 EQU SMBMemBank3 + 0x18 ;/* Status register */
SMB093WstBRdR3 EQU SMBMemBank3 + 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* SSMC Register Offsets for Memory Bank 4 */
SMBMemBank4 EQU SMBMemBank3 + 0x20
SMB093IDCYR4 EQU SMBMemBank4 + 0x00 ;/* Idle-cycle control register */
SMB093WStRdR4 EQU SMBMemBank4 + 0x04 ;/* Wait state Read control register */
SMB093WStWrR4 EQU SMBMemBank4 + 0x08 ;/* Wait state Write control register */
SMB093WSTOENR4 EQU SMBMemBank4 + 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR4 EQU SMBMemBank4 + 0x10 ;/* Write enable assertion delay control register */
SMB093CR4 EQU SMBMemBank4 + 0x14 ;/* Control register */
SMB093SR4 EQU SMBMemBank4 + 0x18 ;/* Status register */
SMB093WstBRdR4 EQU SMBMemBank4 + 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* SSMC Register Offsets for Memory Bank 5 */
SMBMemBank5 EQU SMBMemBank4 + 0x20
SMB093IDCYR5 EQU SMBMemBank5 + 0x00 ;/* Idle-cycle control register */
SMB093WStRdR5 EQU SMBMemBank5 + 0x04 ;/* Wait state Read control register */
SMB093WStWrR5 EQU SMBMemBank5 + 0x08 ;/* Wait state Write control register */
SMB093WSTOENR5 EQU SMBMemBank5 + 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR5 EQU SMBMemBank5 + 0x10 ;/* Write enable assertion delay control register */
SMB093CR5 EQU SMBMemBank5 + 0x14 ;/* Control register */
SMB093SR5 EQU SMBMemBank5 + 0x18 ;/* Status register */
SMB093WstBRdR5 EQU SMBMemBank5 + 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* SSMC Register Offsets for Memory Bank 6 */
SMBMemBank6 EQU SMBMemBank5 + 0x20
SMB093IDCYR6 EQU SMBMemBank6 + 0x00 ;/* Idle-cycle control register */
SMB093WStRdR6 EQU SMBMemBank6 + 0x04 ;/* Wait state Read control register */
SMB093WStWrR6 EQU SMBMemBank6 + 0x08 ;/* Wait state Write control register */
SMB093WSTOENR6 EQU SMBMemBank6 + 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR6 EQU SMBMemBank6 + 0x10 ;/* Write enable assertion delay control register */
SMB093CR6 EQU SMBMemBank6 + 0x14 ;/* Control register */
SMB093SR6 EQU SMBMemBank6 + 0x18 ;/* Status register */
SMB093WstBRdR6 EQU SMBMemBank6 + 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* SSMC Register Offsets for Memory Bank 7 */
SMBMemBank7 EQU SMBMemBank6 + 0x20
SMB093IDCYR7 EQU SMBMemBank7 + 0x00 ;/* Idle-cycle control register */
SMB093WStRdR7 EQU SMBMemBank7 + 0x04 ;/* Wait state Read control register */
SMB093WStWrR7 EQU SMBMemBank7 + 0x08 ;/* Wait state Write control register */
SMB093WSTOENR7 EQU SMBMemBank7 + 0x0C ;/* Output enable assertion delay control register */
SMB093WSTWENR7 EQU SMBMemBank7 + 0x10 ;/* Write enable assertion delay control register */
SMB093CR7 EQU SMBMemBank7 + 0x14 ;/* Control register */
SMB093SR7 EQU SMBMemBank7 + 0x18 ;/* Status register */
SMB093WstBRdR7 EQU SMBMemBank7 + 0x1C ;/* Wait State (Burst Read) Control Reg */
;/* General SSMC Control Register */
SMB093SSMCSR EQU 0x200 ;/* External Wait Status register */
SMB093SSMCCR EQU 0x204 ;/* SSMC Control Register */
;/*************************************************************************************/
;/* */
;/* Bits for General SSMC Control Register (SSMCCR) */
;/* These can be used for any memory bank configuration */
;/* */
;/*************************************************************************************/
SMB093SMCClockEn EQU 0x01 ;/* [0] Clock always running */
SMB093SMCClockSw EQU 0x00 ;/* [0] Clock active only when memory access */
SMB093MemClkRatio1_1 EQU 0x00 ;/* [1:2] SMMEMCLK = HCLK (Default)*/
SMB093MemClkRatio1_2 EQU 0x02 ;/* [1:2] SMMEMCLK = HCLK/2 */
SMB093MemClkRatio1_3 EQU 0x04 ;/* [1:2] SMMEMCLK = HCLK/3 */
SMB093MemClkRatioRsrvd EQU 0x06 ;/* [1:2] reserved */
;/*************************************************************************************/
;/* */
;/* Bits for SSMC Memory Bank Control Register (SMB093SRX) */
;/* These can be used for any memory bank configuration */
;/* */
;/*************************************************************************************/
;/* General Configuration settings */
SMB093CR_RBLE_Low EQU 0x01 ;/* [0] Read byte lane enable, asserted LOW */
SMB093CR_RBLE_High EQU 0x00 ;/* [0] Read byte lane enable, deasserted HIGH */
SMB093CR_WaitPol_Low EQU 0x00 ;/* [1] Polarity of external wait input, LOW active */
SMB093CR_WaitPol_High EQU 0x02 ;/* [1] Polarity of external wait input, HIGH active */
SMB093CR_WaitEn_Low EQU 0x00 ;/* [2] Wait signal disabled */
SMB093CR_WaitEn_High EQU 0x04 ;/* [2] Wait signal enabled, SSMC looks for wait signal SMWAIT */
SMB093CR_WP_Disabled EQU 0x00 ;/* [3] Write protection disabled */
SMB093CR_WP_Enabled EQU 0x08 ;/* [3] Write protection enabled */
SMB093CR_MW_8BIT EQU 0x00 ;/* [5:4] Memory width 8-bits */
SMB093CR_MW_16BIT EQU 0x10 ;/* [5:4] Memory width 16-bits */
SMB093CR_MW_32BIT EQU 0x20 ;/* [5:4] Memory width 32-bits */
SMB093CR_SMLSSPOL_Low EQU 0x00 ;/* [6] Polarity of nSMBLS, LOW active */
SMB093CR_SMLSSPOL_High EQU 0x40 ;/* [6] Polarity of nSMBLS, HIGH active */
;/* [7] reserved */
;/* Burst Mode Read Settings */
SMB093CR_BmRd_Dis EQU 0x0000 ;/* [8] Burst mode Read disabled */
SMB093CR_BmRd_En EQU 0x0100 ;/* [8] Burst mode Read enabled */
SMB093CR_BmRd_Sync_Async EQU 0x0000 ;/* [9] Async (default) */
SMB093CR_BmRd_Sync_Sync EQU 0x0200 ;/* [9] Sync */
SMB093CR_BmRd_Len4 EQU 0x0000 ;/* [11:10] 4 Transfer Burst */
SMB093CR_BmRd_Len8 EQU 0x0400 ;/* [11:10] 8 Transfer Burst */
SMB093CR_BmRd_Len16 EQU 0x0800 ;/* [11:10] 16 Transfer Burst */
SMB093CR_BmRd_LenCont EQU 0x0C00 ;/* [11:10] Continuous Burst (sync only)*/
SMB093CR_BmRd_AddrValDis EQU 0x00000 ;/* [12] SMADDRVALID always HIGH */
SMB093CR_BmRd_AddrValEn EQU 0x01000 ;/* [12] SMADDRVALID active for sync and async read (default) */
SMB093CR_BmRd_BiDis EQU 0x00000 ;/* [13] SMBAA ==1 at all times */
SMB093CR_BmRd_BiEn EQU 0x02000 ;/* [13] SMBAA active for read access */
SMB093CR_BmRd_WrapDis EQU 0x00000 ;/* [14] Wrap Read (default) */
SMB093CR_BmRd_WrapEn EQU 0x04000 ;/* [14] Wrap Read, Burst mode in 8 word bursts */
;/* [15] reserved */
;/* Burst Mode Write Settings */
SMB093CR_BmWr_Dis EQU 0x000000 ;/* [16] Burst mode Write disabled */
SMB093CR_BmWr_En EQU 0x010000 ;/* [16] Burst mode Write enabled */
SMB093CR_BmWr_Sync_Async EQU 0x000000 ;/* [17] Async (default) */
SMB093CR_BmWr_Sync_Sync EQU 0x020000 ;/* [17] Sync */
SMB093CR_BmWr_Len4 EQU 0x000000 ;/* [19:18] 4 Transfer Burst */
SMB093CR_BmWr_Len8 EQU 0x040000 ;/* [19:18] 8 Transfer Burst */
SMB093CR_BmWr_LenRsrv EQU 0x080000 ;/* [19:18] Reserved */
SMB093CR_BmWr_LenCont EQU 0x0C0000 ;/* [19:18] Continuous Burst */
SMB093CR_BmWr_AddrValDis EQU 0x000000 ;/* [20] SMADDRVALID always HIGH */
SMB093CR_BmWr_AddrValEn EQU 0x100000 ;/* [20] SMADDRVALID active for sync and async write (default) */
SMB093CR_BmWr_BiDis EQU 0x000000 ;/* [21] SMBAA ==1 at all times */
SMB093CR_BmWr_BiEn EQU 0x200000 ;/* [21] SMBAA active for write access */
;/*************************************************************************************/
;/* */
;/* Bits for SSMC Bank Status Register (SMB093SRX) */
;/* These can be used for any memory bank configuration */
;/* */
;/*************************************************************************************/
SMB093SR_WaitToutErr_NOERR EQU 0x00 ;/* [0] External wait timeout error flag */
SMB093SR_WaitToutErr_ERR EQU 0x01
SMB093SR_ErrorFlags EQU SMB093SR_WaitToutErr_ERR
ENDIF ; ssmc_inc
END
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