📄 cpld4gdf.rpt
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-- Node name is 'L2' = '|74273:69|Q2'
-- Equation name is 'L2', type is output
L2 = DFFE( RD1 $ GND, _EQ014, !SWRESET, VCC, VCC);
_EQ014 = _X002;
_X002 = EXP( A2 & A3 & !A15 & !/IOS);
-- Node name is 'L3' = '|74273:69|Q3'
-- Equation name is 'L3', type is output
L3 = DFFE( RD2 $ GND, _EQ015, !SWRESET, VCC, VCC);
_EQ015 = _X002;
_X002 = EXP( A2 & A3 & !A15 & !/IOS);
-- Node name is 'L4' = '|74273:69|Q4'
-- Equation name is 'L4', type is output
L4 = DFFE( RD3 $ GND, _EQ016, !SWRESET, VCC, VCC);
_EQ016 = _X002;
_X002 = EXP( A2 & A3 & !A15 & !/IOS);
-- Node name is 'L5' = '|74273:69|Q5'
-- Equation name is 'L5', type is output
L5 = DFFE( RD4 $ GND, _EQ017, !SWRESET, VCC, VCC);
_EQ017 = _X002;
_X002 = EXP( A2 & A3 & !A15 & !/IOS);
-- Node name is 'L6' = '|74273:69|Q6'
-- Equation name is 'L6', type is output
L6 = DFFE( RD5 $ GND, _EQ018, !SWRESET, VCC, VCC);
_EQ018 = _X002;
_X002 = EXP( A2 & A3 & !A15 & !/IOS);
-- Node name is 'L7' = '|74273:69|Q7'
-- Equation name is 'L7', type is output
L7 = DFFE( RD6 $ GND, _EQ019, !SWRESET, VCC, VCC);
_EQ019 = _X002;
_X002 = EXP( A2 & A3 & !A15 & !/IOS);
-- Node name is 'L8' = '|74273:69|Q8'
-- Equation name is 'L8', type is output
L8 = DFFE( RD7 $ GND, _EQ020, !SWRESET, VCC, VCC);
_EQ020 = _X002;
_X002 = EXP( A2 & A3 & !A15 & !/IOS);
-- Node name is 'RD0'
-- Equation name is 'RD0', location is LC008, type is bidir.
RD0 = TRI(_LC008, _LC069);
_LC008 = LCELL( K0 $ GND);
-- Node name is 'RD1'
-- Equation name is 'RD1', location is LC009, type is bidir.
RD1 = TRI(_LC009, _LC069);
_LC009 = LCELL( K1 $ GND);
-- Node name is 'RD2'
-- Equation name is 'RD2', location is LC011, type is bidir.
RD2 = TRI(_LC011, _LC069);
_LC011 = LCELL( K2 $ GND);
-- Node name is 'RD3'
-- Equation name is 'RD3', location is LC012, type is bidir.
RD3 = TRI(_LC012, _LC069);
_LC012 = LCELL( K3 $ GND);
-- Node name is 'RD4'
-- Equation name is 'RD4', location is LC013, type is bidir.
RD4 = TRI(_LC013, _LC069);
_LC013 = LCELL( K4 $ GND);
-- Node name is 'RD5'
-- Equation name is 'RD5', location is LC014, type is bidir.
RD5 = TRI(_LC014, _LC069);
_LC014 = LCELL( K5 $ GND);
-- Node name is 'RD6'
-- Equation name is 'RD6', location is LC016, type is bidir.
RD6 = TRI(_LC016, _LC069);
_LC016 = LCELL( K6 $ GND);
-- Node name is 'RD7~1'
-- Equation name is 'RD7~1', location is LC069, type is buried.
-- synthesized logic cell
_LC069 = LCELL( _EQ021 $ GND);
_EQ021 = A0 & A1 & !A2 & A3 & !A15 & !/IOS;
-- Node name is 'RD7'
-- Equation name is 'RD7', location is LC128, type is bidir.
RD7 = TRI(_LC128, _LC069);
_LC128 = LCELL( K7 $ GND);
-- Node name is 'SD0' = '|74374:99|:13'
-- Equation name is 'SD0', type is output
SD0 = TRI(_LC076, _LC067);
_LC076 = DFFE( D0 $ GND, _EQ022, VCC, VCC, VCC);
_EQ022 = _X003;
_X003 = EXP( A0 & !A1 & A2 & !A3 & !A15 & !/IOS & !/WE);
-- Node name is 'SD1' = '|74374:99|:14'
-- Equation name is 'SD1', type is output
SD1 = TRI(_LC075, _LC067);
_LC075 = DFFE( D1 $ GND, _EQ023, VCC, VCC, VCC);
_EQ023 = _X003;
_X003 = EXP( A0 & !A1 & A2 & !A3 & !A15 & !/IOS & !/WE);
-- Node name is 'SD2' = '|74374:99|:15'
-- Equation name is 'SD2', type is output
SD2 = TRI(_LC073, _LC067);
_LC073 = DFFE( D2 $ GND, _EQ024, VCC, VCC, VCC);
_EQ024 = _X003;
_X003 = EXP( A0 & !A1 & A2 & !A3 & !A15 & !/IOS & !/WE);
-- Node name is 'SD3' = '|74374:99|:16'
-- Equation name is 'SD3', type is output
SD3 = TRI(_LC072, _LC067);
_LC072 = DFFE( D3 $ GND, _EQ025, VCC, VCC, VCC);
_EQ025 = _X003;
_X003 = EXP( A0 & !A1 & A2 & !A3 & !A15 & !/IOS & !/WE);
-- Node name is 'UD0'
-- Equation name is 'UD0', location is LC124, type is bidir.
UD0 = TRI(_LC124, _LC035);
_LC124 = LCELL( _EQ026 $ GND);
_EQ026 = !A2 & !A3 & !A14 & A15 & D7 & !/IOS;
-- Node name is 'UD1'
-- Equation name is 'UD1', location is LC123, type is bidir.
UD1 = TRI(_LC123, _LC035);
_LC123 = LCELL( _EQ027 $ GND);
_EQ027 = !A2 & !A3 & !A14 & A15 & D6 & !/IOS;
-- Node name is 'UD2'
-- Equation name is 'UD2', location is LC121, type is bidir.
UD2 = TRI(_LC121, _LC035);
_LC121 = LCELL( _EQ028 $ GND);
_EQ028 = !A2 & !A3 & !A14 & A15 & D5 & !/IOS;
-- Node name is 'UD3'
-- Equation name is 'UD3', location is LC120, type is bidir.
UD3 = TRI(_LC120, _LC035);
_LC120 = LCELL( _EQ029 $ GND);
_EQ029 = !A2 & !A3 & !A14 & A15 & D4 & !/IOS;
-- Node name is 'UD4'
-- Equation name is 'UD4', location is LC118, type is bidir.
UD4 = TRI(_LC118, _LC035);
_LC118 = LCELL( _EQ030 $ GND);
_EQ030 = !A2 & !A3 & !A14 & A15 & D3 & !/IOS;
-- Node name is 'UD5'
-- Equation name is 'UD5', location is LC117, type is bidir.
UD5 = TRI(_LC117, _LC035);
_LC117 = LCELL( _EQ031 $ GND);
_EQ031 = !A2 & !A3 & !A14 & A15 & D2 & !/IOS;
-- Node name is 'UD6'
-- Equation name is 'UD6', location is LC116, type is bidir.
UD6 = TRI(_LC116, _LC035);
_LC116 = LCELL( _EQ032 $ GND);
_EQ032 = !A2 & !A3 & !A14 & A15 & D1 & !/IOS;
-- Node name is 'UD7~1'
-- Equation name is 'UD7~1', location is LC035, type is buried.
-- synthesized logic cell
_LC035 = LCELL( _EQ033 $ GND);
_EQ033 = !A2 & !A3 & !A14 & A15 & !/IOS;
-- Node name is 'UD7'
-- Equation name is 'UD7', location is LC115, type is bidir.
UD7 = TRI(_LC115, _LC035);
_LC115 = LCELL( _EQ034 $ GND);
_EQ034 = !A2 & !A3 & !A14 & A15 & D0 & !/IOS;
-- Node name is '|74374:99|~16~1'
-- Equation name is '_LC067', type is buried
-- synthesized logic cell
_LC067 = LCELL( _EQ035 $ GND);
_EQ035 = A0 & !A1 & A2 & !A3 & !A15 & !/IOS;
-- Node name is '/BUFFER'
-- Equation name is '/BUFFER', location is LC005, type is output.
/BUFFER = LCELL( _EQ036 $ VCC);
_EQ036 = A0 & A1 & !A2 & A3 & !A15 & !/IOS & !/STRB
# A2 & A3 & !A15 & !/IOS & !/STRB
# !A2 & !A3 & !A15 & !/IOS & !/STRB;
-- Node name is '/CDR'
-- Equation name is '/CDR', location is LC099, type is output.
/CDR = LCELL( _EQ037 $ VCC);
_EQ037 = A0 & !A1 & !A2 & A3 & !A15 & !/IOS & !/RD;
-- Node name is '/CDW'
-- Equation name is '/CDW', location is LC097, type is output.
/CDW = LCELL( _EQ038 $ VCC);
_EQ038 = A0 & !A1 & !A2 & A3 & !A15 & !/IOS & !/WE;
-- Node name is '/DACS'
-- Equation name is '/DACS', location is LC004, type is output.
/DACS = LCELL( _EQ039 $ VCC);
_EQ039 = !A2 & !A3 & !A15 & !/IOS;
-- Node name is '/LCE'
-- Equation name is '/LCE', location is LC094, type is output.
/LCE = LCELL( CAP2/QEP2/IOPA4 $ GND);
-- Node name is '/RAMOE'
-- Equation name is '/RAMOE', location is LC029, type is output.
/RAMOE = LCELL( _EQ040 $ /RD);
_EQ040 = /DS & /PS & !/RD;
-- Node name is '/RAMWE'
-- Equation name is '/RAMWE', location is LC030, type is output.
/RAMWE = LCELL( _EQ041 $ /WE);
_EQ041 = /DS & /PS & !/WE;
-- Node name is '/RS'
-- Equation name is '/RS', location is LC021, type is output.
/RS = LCELL(!SWRESET $ GND);
-- Node name is '/UCS'
-- Equation name is '/UCS', location is LC113, type is output.
/UCS = LCELL( _EQ042 $ GND);
_EQ042 = !A2 & !A3 & !A14 & A15 & !/IOS;
-- Node name is '/UOE'
-- Equation name is '/UOE', location is LC125, type is output.
/UOE = LCELL( _EQ043 $ VCC);
_EQ043 = !A12 & !A13 & !A14 & A15 & !/IOS & !/RD;
-- Node name is '/UWE'
-- Equation name is '/UWE', location is LC126, type is output.
/UWE = LCELL( _EQ044 $ VCC);
_EQ044 = !A12 & !A13 & !A14 & A15 & !/IOS & !/WE;
-- Node name is '/XFER'
-- Equation name is '/XFER', location is LC006, type is output.
/XFER = LCELL( _EQ045 $ VCC);
_EQ045 = !A2 & A3 & !A15 & !/IOS;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\cpldnew\cpld4gdf.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:05
-------------------------- --------
Total Time 00:00:10
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,162K
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