cpld4gdf.rpt

用maxplus2实现的一种通用逻辑模块

Device-Specific Information:                           e:\cpldnew\cpld4gdf.rpt
cpld4gdf

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                       Logic cells placed in LAB 'E'
        +------------- LC80 BD5~1
        | +----------- LC69 RD7~1
        | | +--------- LC76 SD0
        | | | +------- LC75 SD1
        | | | | +----- LC73 SD2
        | | | | | +--- LC72 SD3
        | | | | | | +- LC67 |74374:99|~16~1
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':

Pin
31   -> - * * * * * * | * - - * * - * - | <-- A0
30   -> * * * * * * * | * - - * * - * - | <-- A1
29   -> * * * * * * * | * - * * * * * * | <-- A2
28   -> * * * * * * * | * - * * * * * * | <-- A3
23   -> * * * * * * * | * - * * * * * * | <-- A15
51   -> * * * * * * * | * - * * * * * * | <-- /IOS
43   -> - - * * * * - | * * - - * - * * | <-- /WE
LC17 -> - - * - - - - | - - - - * - * * | <-- D0
LC19 -> - - - * - - - | - - - - * - * * | <-- D1
LC20 -> - - - - * - - | - - - - * - * * | <-- D2
LC22 -> - - - - - * - | - - - - * - * * | <-- D3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\cpldnew\cpld4gdf.rpt
cpld4gdf

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                           Logic cells placed in LAB 'F'
        +----------------- LC94 /LCE
        | +--------------- LC93 L1
        | | +------------- LC92 L2
        | | | +----------- LC91 L3
        | | | | +--------- LC89 L4
        | | | | | +------- LC88 L5
        | | | | | | +----- LC86 L6
        | | | | | | | +--- LC85 L7
        | | | | | | | | +- LC84 L8
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':

Pin
29   -> - * * * * * * * * | * - * * * * * * | <-- A2
28   -> - * * * * * * * * | * - * * * * * * | <-- A3
23   -> - * * * * * * * * | * - * * * * * * | <-- A15
53   -> * - - - - - - - - | - - - - - * - - | <-- CAP2/QEP2/IOPA4
51   -> - * * * * * * * * | * - * * * * * * | <-- /IOS
52   -> - * * * * * * * * | - * - - - * - - | <-- SWRESET
LC8  -> - * - - - - - - - | - - - - - * - - | <-- RD0
LC9  -> - - * - - - - - - | - - - - - * - - | <-- RD1
LC11 -> - - - * - - - - - | - - - - - * - - | <-- RD2
LC12 -> - - - - * - - - - | - - - - - * - - | <-- RD3
LC13 -> - - - - - * - - - | - - - - - * - - | <-- RD4
LC14 -> - - - - - - * - - | - - - - - * - - | <-- RD5
LC16 -> - - - - - - - * - | - - - - - * - - | <-- RD6
LC128-> - - - - - - - - * | - - - - - * - - | <-- RD7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\cpldnew\cpld4gdf.rpt
cpld4gdf

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                               Logic cells placed in LAB 'G'
        +--------------------- LC110 BD0
        | +------------------- LC109 BD1
        | | +----------------- LC108 BD2
        | | | +--------------- LC107 BD3
        | | | | +------------- LC105 BD4
        | | | | | +----------- LC104 BD5
        | | | | | | +--------- LC102 BD6
        | | | | | | | +------- LC101 BD7
        | | | | | | | | +----- LC99 /CDR
        | | | | | | | | | +--- LC97 /CDW
        | | | | | | | | | | +- LC100 LC/D
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
31   -> - - - - - - - - * * * | * - - * * - * - | <-- A0
30   -> * * * * * * * * * * - | * - - * * - * - | <-- A1
29   -> * * * * * * * * * * - | * - * * * * * * | <-- A2
28   -> * * * * * * * * * * - | * - * * * * * * | <-- A3
23   -> * * * * * * * * * * - | * - * * * * * * | <-- A15
51   -> * * * * * * * * * * - | * - * * * * * * | <-- /IOS
41   -> - - - - - - - - * - - | - * - * - - * * | <-- /RD
43   -> - - - - - - - - - * - | * * - - * - * * | <-- /WE
LC17 -> * - - - - - - - - - - | - - - - * - * * | <-- D0
LC19 -> - * - - - - - - - - - | - - - - * - * * | <-- D1
LC20 -> - - * - - - - - - - - | - - - - * - * * | <-- D2
LC22 -> - - - * - - - - - - - | - - - - * - * * | <-- D3
LC24 -> - - - - * - - - - - - | - - - - - - * * | <-- D4
LC25 -> - - - - - * - - - - - | - - - - - - * * | <-- D5
LC27 -> - - - - - - * - - - - | - - - - - - * * | <-- D6
LC28 -> - - - - - - - * - - - | - - - - - - * * | <-- D7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\cpldnew\cpld4gdf.rpt
cpld4gdf

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                 Logic cells placed in LAB 'H'
        +----------------------- LC128 RD7
        | +--------------------- LC113 /UCS
        | | +------------------- LC124 UD0
        | | | +----------------- LC123 UD1
        | | | | +--------------- LC121 UD2
        | | | | | +------------- LC120 UD3
        | | | | | | +----------- LC118 UD4
        | | | | | | | +--------- LC117 UD5
        | | | | | | | | +------- LC116 UD6
        | | | | | | | | | +----- LC115 UD7
        | | | | | | | | | | +--- LC125 /UOE
        | | | | | | | | | | | +- LC126 /UWE
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':

Pin
29   -> - * * * * * * * * * - - | * - * * * * * * | <-- A2
28   -> - * * * * * * * * * - - | * - * * * * * * | <-- A3
27   -> - - - - - - - - - - * * | - - - - - - - * | <-- A12
25   -> - - - - - - - - - - * * | - - - - - - - * | <-- A13
24   -> - * * * * * * * * * * * | - - * - - - - * | <-- A14
23   -> - * * * * * * * * * * * | * - * * * * * * | <-- A15
51   -> - * * * * * * * * * * * | * - * * * * * * | <-- /IOS
67   -> * - - - - - - - - - - - | - - - - - - - * | <-- K7
41   -> - - - - - - - - - - * - | - * - * - - * * | <-- /RD
43   -> - - - - - - - - - - - * | * * - - * - * * | <-- /WE
LC17 -> - - - - - - - - - * - - | - - - - * - * * | <-- D0
LC19 -> - - - - - - - - * - - - | - - - - * - * * | <-- D1
LC20 -> - - - - - - - * - - - - | - - - - * - * * | <-- D2
LC22 -> - - - - - - * - - - - - | - - - - * - * * | <-- D3
LC24 -> - - - - - * - - - - - - | - - - - - - * * | <-- D4
LC25 -> - - - - * - - - - - - - | - - - - - - * * | <-- D5
LC27 -> - - - * - - - - - - - - | - - - - - - * * | <-- D6
LC28 -> - - * - - - - - - - - - | - - - - - - * * | <-- D7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\cpldnew\cpld4gdf.rpt
cpld4gdf

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A12      : INPUT;
A13      : INPUT;
A14      : INPUT;
A15      : INPUT;
CAP1/QEP1/IOPA3 : INPUT;
CAP2/QEP2/IOPA4 : INPUT;
CAP3/IOPA5 : INPUT;
CAP4/QEP3/IOPE7 : INPUT;
HOSTRESET : INPUT;
K0       : INPUT;
K1       : INPUT;
K2       : INPUT;
K3       : INPUT;
K4       : INPUT;
K5       : INPUT;
K6       : INPUT;
K7       : INPUT;
SD4      : INPUT;
SD5      : INPUT;
SD6      : INPUT;
SD7      : INPUT;
SWRESET  : INPUT;
TEFREST  : INPUT;
/DS      : INPUT;
/IOS     : INPUT;
/PS      : INPUT;
/PWRONRST : INPUT;
/RD      : INPUT;
/STRB    : INPUT;
/WE      : INPUT;

-- Node name is 'BD0' 
-- Equation name is 'BD0', location is LC110, type is bidir.
BD0      = TRI(_LC110,  _LC080);
_LC110   = LCELL( _EQ001 $  GND);
  _EQ001 = !A1 & !A2 &  A3 & !A15 &  D0 & !/IOS;

-- Node name is 'BD1' 
-- Equation name is 'BD1', location is LC109, type is bidir.
BD1      = TRI(_LC109,  _LC080);
_LC109   = LCELL( _EQ002 $  GND);
  _EQ002 = !A1 & !A2 &  A3 & !A15 &  D1 & !/IOS;

-- Node name is 'BD2' 
-- Equation name is 'BD2', location is LC108, type is bidir.
BD2      = TRI(_LC108,  _LC080);
_LC108   = LCELL( _EQ003 $  GND);
  _EQ003 = !A1 & !A2 &  A3 & !A15 &  D2 & !/IOS;

-- Node name is 'BD3' 
-- Equation name is 'BD3', location is LC107, type is bidir.
BD3      = TRI(_LC107,  _LC080);
_LC107   = LCELL( _EQ004 $  GND);
  _EQ004 = !A1 & !A2 &  A3 & !A15 &  D3 & !/IOS;

-- Node name is 'BD4' 
-- Equation name is 'BD4', location is LC105, type is bidir.
BD4      = TRI(_LC105,  _LC080);
_LC105   = LCELL( _EQ005 $  GND);
  _EQ005 = !A1 & !A2 &  A3 & !A15 &  D4 & !/IOS;

-- Node name is 'BD5~1' 
-- Equation name is 'BD5~1', location is LC080, type is buried.
-- synthesized logic cell 
_LC080   = LCELL( _EQ006 $  GND);
  _EQ006 = !A1 & !A2 &  A3 & !A15 & !/IOS;

-- Node name is 'BD5' 
-- Equation name is 'BD5', location is LC104, type is bidir.
BD5      = TRI(_LC104,  _LC080);
_LC104   = LCELL( _EQ007 $  GND);
  _EQ007 = !A1 & !A2 &  A3 & !A15 &  D5 & !/IOS;

-- Node name is 'BD6' 
-- Equation name is 'BD6', location is LC102, type is bidir.
BD6      = TRI(_LC102,  _LC080);
_LC102   = LCELL( _EQ008 $  GND);
  _EQ008 = !A1 & !A2 &  A3 & !A15 &  D6 & !/IOS;

-- Node name is 'BD7' 
-- Equation name is 'BD7', location is LC101, type is bidir.
BD7      = TRI(_LC101,  _LC080);
_LC101   = LCELL( _EQ009 $  GND);
  _EQ009 = !A1 & !A2 &  A3 & !A15 &  D7 & !/IOS;

-- Node name is 'CON_INTSW' = ':3' 
-- Equation name is 'CON_INTSW', type is output 
 CON_INTSW = DFFE( GND $  VCC,  _EQ010, !_EQ011,  VCC,  VCC);
  _EQ010 =  SD4 &  SD5 &  SD6 &  SD7;
  _EQ011 =  _X001;
  _X001  = EXP(!A0 &  A1 &  A2 & !A3 & !A15 & !/IOS & !/WE);

-- Node name is 'D0' 
-- Equation name is 'D0', location is LC017, type is bidir.
D0       = TRI(_LC017,  _LC051);
_LC017   = LCELL( GND $  VCC);

-- Node name is 'D1' 
-- Equation name is 'D1', location is LC019, type is bidir.
D1       = TRI(_LC019,  _LC051);
_LC019   = LCELL( GND $  VCC);

-- Node name is 'D2' 
-- Equation name is 'D2', location is LC020, type is bidir.
D2       = TRI(_LC020,  _LC051);
_LC020   = LCELL( GND $  VCC);

-- Node name is 'D3' 
-- Equation name is 'D3', location is LC022, type is bidir.
D3       = TRI(_LC022,  _LC051);
_LC022   = LCELL( GND $  VCC);

-- Node name is 'D4' 
-- Equation name is 'D4', location is LC024, type is bidir.
D4       = TRI(_LC024,  _LC051);
_LC024   = LCELL( SD4 $  GND);

-- Node name is 'D5' 
-- Equation name is 'D5', location is LC025, type is bidir.
D5       = TRI(_LC025,  _LC051);
_LC025   = LCELL( SD5 $  GND);

-- Node name is 'D6~1' 
-- Equation name is 'D6~1', location is LC051, type is buried.
-- synthesized logic cell 
_LC051   = LCELL( _EQ012 $  GND);
  _EQ012 =  A0 & !A1 &  A2 & !A3 & !A15 & !/IOS & !/RD;

-- Node name is 'D6' 
-- Equation name is 'D6', location is LC027, type is bidir.
D6       = TRI(_LC027,  _LC051);
_LC027   = LCELL( SD6 $  GND);

-- Node name is 'D7' 
-- Equation name is 'D7', location is LC028, type is bidir.
D7       = TRI(_LC028,  _LC051);
_LC028   = LCELL( SD7 $  GND);

-- Node name is 'LC/D' 
-- Equation name is 'LC/D', location is LC100, type is output.
 LC/D    = LCELL( A0 $  GND);

-- Node name is 'L1' = '|74273:69|Q1' 
-- Equation name is 'L1', type is output 
 L1      = DFFE( RD0 $  GND,  _EQ013, !SWRESET,  VCC,  VCC);
  _EQ013 =  _X002;
  _X002  = EXP( A2 &  A3 & !A15 & !/IOS);