📄 cpld4gdf.rpt
字号:
Project Information e:\cpldnew\cpld4gdf.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 03/07/2006 15:59:21
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
cpld4gdf EPM7128SQC160-15 34 26 32 63 3 49 %
User Pins: 34 26 32
Project Information e:\cpldnew\cpld4gdf.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored primitive symbol "TRI" (ID :184) it has no output
Warning: Ignored primitive symbol "TRI" (ID :181) it has no output
Warning: Ignored primitive symbol "TRI" (ID :178) it has no output
Info: Reserved unused input pin 'CAP4/QEP3/IOPE7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'CAP1/QEP1/IOPA3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'CAP3/IOPA5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'HOSTRESET' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin '/PWRONRST' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'TEFREST' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information e:\cpldnew\cpld4gdf.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
cpld4gdf@31 A0
cpld4gdf@30 A1
cpld4gdf@29 A2
cpld4gdf@28 A3
cpld4gdf@27 A12
cpld4gdf@25 A13
cpld4gdf@24 A14
cpld4gdf@23 A15
cpld4gdf@111 BD0
cpld4gdf@110 BD1
cpld4gdf@109 BD2
cpld4gdf@108 BD3
cpld4gdf@107 BD4
cpld4gdf@106 BD5
cpld4gdf@105 BD6
cpld4gdf@103 BD7
cpld4gdf@153 /BUFFER
cpld4gdf@50 CAP1/QEP1/IOPA3
cpld4gdf@53 CAP2/QEP2/IOPA4
cpld4gdf@54 CAP3/IOPA5
cpld4gdf@32 CAP4/QEP3/IOPE7
cpld4gdf@101 /CDR
cpld4gdf@100 /CDW
cpld4gdf@159 CON_INTSW
cpld4gdf@158 /DACS
cpld4gdf@48 /DS
cpld4gdf@21 D0
cpld4gdf@20 D1
cpld4gdf@19 D2
cpld4gdf@16 D3
cpld4gdf@15 D4
cpld4gdf@14 D5
cpld4gdf@13 D6
cpld4gdf@12 D7
cpld4gdf@160 HOSTRESET
cpld4gdf@51 /IOS
cpld4gdf@57 K0
cpld4gdf@58 K1
cpld4gdf@59 K2
cpld4gdf@62 K3
cpld4gdf@63 K4
cpld4gdf@64 K5
cpld4gdf@65 K6
cpld4gdf@67 K7
cpld4gdf@102 LC/D
cpld4gdf@98 /LCE
cpld4gdf@97 L1
cpld4gdf@96 L2
cpld4gdf@94 L3
cpld4gdf@93 L4
cpld4gdf@92 L5
cpld4gdf@91 L6
cpld4gdf@90 L7
cpld4gdf@89 L8
cpld4gdf@49 /PS
cpld4gdf@88 /PWRONRST
cpld4gdf@11 /RAMOE
cpld4gdf@10 /RAMWE
cpld4gdf@41 /RD
cpld4gdf@151 RD0
cpld4gdf@150 RD1
cpld4gdf@149 RD2
cpld4gdf@147 RD3
cpld4gdf@146 RD4
cpld4gdf@145 RD5
cpld4gdf@144 RD6
cpld4gdf@137 RD7
cpld4gdf@18 /RS
cpld4gdf@71 SD0
cpld4gdf@70 SD1
cpld4gdf@69 SD2
cpld4gdf@68 SD3
cpld4gdf@72 SD4
cpld4gdf@73 SD5
cpld4gdf@78 SD6
cpld4gdf@80 SD7
cpld4gdf@33 /STRB
cpld4gdf@52 SWRESET
cpld4gdf@56 TEFREST
cpld4gdf@121 /UCS
cpld4gdf@134 UD0
cpld4gdf@132 UD1
cpld4gdf@131 UD2
cpld4gdf@130 UD3
cpld4gdf@129 UD4
cpld4gdf@128 UD5
cpld4gdf@123 UD6
cpld4gdf@122 UD7
cpld4gdf@135 /UOE
cpld4gdf@136 /UWE
cpld4gdf@43 /WE
cpld4gdf@152 /XFER
Project Information e:\cpldnew\cpld4gdf.rpt
** FILE HIERARCHY **
|74273:69|
|74244:68|
|74244:105|
|tri_gate:171|
|tri_gate:172|
|74374:99|
|u11:174|
|u11:174|u1:121|
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
***** Logic for device 'cpld4gdf' compiled without errors.
Device: EPM7128SQC160-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** ERROR SUMMARY **
Info: Chip 'cpld4gdf' in device 'EPM7128SQC160-15' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
H C
O O
S N /
T _ B V
R I / U / C V
E N D N N N N F X C / / C N N N N /
S T A . . . . F F R R R G R R R R I G G G G G R U U U C U U U U U . . . . U U U
E S C C C C C E E D D D N D D D D N N N N N N D W O D I D D D D D C C C C D D C
T W S . . . . R R 0 1 2 D 3 4 5 6 T D D D D D 7 E E 0 O 1 2 3 4 5 . . . . 6 7 S
----------------------------------------------------------------------------------_
/ 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 |_
/ 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 |
N.C. | 1 120 | N.C.
N.C. | 2 119 | N.C.
N.C. | 3 118 | N.C.
N.C. | 4 117 | N.C.
N.C. | 5 116 | N.C.
N.C. | 6 115 | N.C.
N.C. | 7 114 | N.C.
VCCIO | 8 113 | GND
#TDI | 9 112 | #TDO
/RAMWE | 10 111 | BD0
/RAMOE | 11 110 | BD1
D7 | 12 109 | BD2
D6 | 13 108 | BD3
D5 | 14 107 | BD4
D4 | 15 106 | BD5
D3 | 16 105 | BD6
GND | 17 104 | VCCIO
/RS | 18 103 | BD7
D2 | 19 102 | LC/D
D1 | 20 101 | /CDR
D0 | 21 EPM7128SQC160-15 100 | /CDW
#TMS | 22 99 | #TCK
A15 | 23 98 | /LCE
A14 | 24 97 | L1
A13 | 25 96 | L2
VCCIO | 26 95 | GND
A12 | 27 94 | L3
A3 | 28 93 | L4
A2 | 29 92 | L5
A1 | 30 91 | L6
A0 | 31 90 | L7
CAP4/QEP3/IOPE7 | 32 89 | L8
/STRB | 33 88 | /PWRONRST
N.C. | 34 87 | N.C.
N.C. | 35 86 | N.C.
N.C. | 36 85 | N.C.
N.C. | 37 84 | N.C.
N.C. | 38 83 | N.C.
N.C. | 39 82 | N.C.
N.C. | 40 81 | N.C.
| 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 _|
\ 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 |
\-----------------------------------------------------------------------------------
/ G / N N N N / / C / S C C V T K K K G V K K K K G K S S S S S S N N N N S V S
R N W . . . . D P A I W A A C E 0 1 2 N C 3 4 5 6 N 7 D D D D D D . . . . D C D
D D E C C C C S S P O R P P C F D C D 3 2 1 0 4 5 C C C C 6 C 7
. . . . 1 S E 2 3 I R I . . . . I
/ S / / O E N O
Q E Q I S T
E T E O T
P P P
1 2 A
/ / 5
I I
O O
P P
A A
3 4
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 11/16( 68%) 12/12(100%) 1/16( 6%) 19/36( 52%)
B: LC17 - LC32 11/16( 68%) 12/12(100%) 0/16( 0%) 9/36( 25%)
C: LC33 - LC48 1/16( 6%) 12/12(100%) 0/16( 0%) 5/36( 13%)
D: LC49 - LC64 1/16( 6%) 12/12(100%) 0/16( 0%) 7/36( 19%)
E: LC65 - LC80 7/16( 43%) 12/12(100%) 1/16( 6%) 11/36( 30%)
F: LC81 - LC96 9/16( 56%) 12/12(100%) 1/16( 6%) 14/36( 38%)
G: LC97 - LC112 11/16( 68%) 12/12(100%) 0/16( 0%) 16/36( 44%)
H: LC113 - LC128 12/16( 75%) 12/12(100%) 0/16( 0%) 18/36( 50%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 96/96 (100%)
Total logic cells used: 63/128 ( 49%)
Total shareable expanders used: 3/128 ( 2%)
Total Turbo logic cells used: 63/128 ( 49%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 5.06
Total fan-in: 319
Total input pins required: 34
Total fast input logic cells required: 0
Total output pins required: 26
Total bidirectional pins required: 32
Total reserved pins required 4
Total logic cells required: 63
Total flipflops required: 13
Total product terms required: 92
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 3
Synthesized logic cells: 5/ 128 ( 3%)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -