📄 cpld4gdf00.tan.rpt
字号:
; N/A ; None ; 15.000 ns ; D5 ; UD2 ;
; N/A ; None ; 15.000 ns ; D4 ; UD3 ;
; N/A ; None ; 15.000 ns ; K[7] ; RD[7] ;
; N/A ; None ; 15.000 ns ; K[6] ; RD[6] ;
; N/A ; None ; 15.000 ns ; K[5] ; RD[5] ;
; N/A ; None ; 15.000 ns ; K[4] ; RD[4] ;
; N/A ; None ; 15.000 ns ; K[3] ; RD[3] ;
; N/A ; None ; 15.000 ns ; K[2] ; RD[2] ;
; N/A ; None ; 15.000 ns ; K[1] ; RD[1] ;
; N/A ; None ; 15.000 ns ; K[0] ; RD[0] ;
; N/A ; None ; 15.000 ns ; SD7 ; D7 ;
; N/A ; None ; 15.000 ns ; SD6 ; D6 ;
; N/A ; None ; 15.000 ns ; SD5 ; D5 ;
; N/A ; None ; 15.000 ns ; SD4 ; D4 ;
; N/A ; None ; 15.000 ns ; /STRB ; /BUFFER ;
; N/A ; None ; 15.000 ns ; A3 ; /DACS ;
; N/A ; None ; 15.000 ns ; A15 ; /DACS ;
; N/A ; None ; 15.000 ns ; A2 ; /DACS ;
; N/A ; None ; 15.000 ns ; /IOS ; /DACS ;
; N/A ; None ; 15.000 ns ; A3 ; /XFER ;
; N/A ; None ; 15.000 ns ; A15 ; /XFER ;
; N/A ; None ; 15.000 ns ; A2 ; /XFER ;
; N/A ; None ; 15.000 ns ; /IOS ; /XFER ;
; N/A ; None ; 15.000 ns ; A14 ; /UCS ;
; N/A ; None ; 15.000 ns ; A3 ; /UCS ;
; N/A ; None ; 15.000 ns ; A15 ; /UCS ;
; N/A ; None ; 15.000 ns ; A2 ; /UCS ;
; N/A ; None ; 15.000 ns ; /IOS ; /UCS ;
; N/A ; None ; 15.000 ns ; TEFREST ; /RS ;
; N/A ; None ; 15.000 ns ; HOSTRESET ; /RS ;
; N/A ; None ; 15.000 ns ; SWRESET ; /RS ;
; N/A ; None ; 15.000 ns ; /PWRONRST ; /RS ;
+-------+-------------------+-----------------+-----------+---------+
+------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-----------------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-----------------+-------------+----------+
; N/A ; None ; 13.000 ns ; CAP1/QEP1/IOPA3 ; 74377:94|32 ; /IOS ;
; N/A ; None ; 13.000 ns ; CAP1/QEP1/IOPA3 ; 74377:94|32 ; A2 ;
; N/A ; None ; 13.000 ns ; CAP1/QEP1/IOPA3 ; 74377:94|32 ; A15 ;
; N/A ; None ; 13.000 ns ; CAP1/QEP1/IOPA3 ; 74377:94|32 ; A3 ;
; N/A ; None ; 13.000 ns ; CAP1/QEP1/IOPA3 ; 74377:94|32 ; A1 ;
; N/A ; None ; 13.000 ns ; CAP1/QEP1/IOPA3 ; 74377:94|32 ; A0 ;
; N/A ; None ; 13.000 ns ; CAP2/QEP2/IOPA4 ; 74377:94|33 ; /IOS ;
; N/A ; None ; 13.000 ns ; CAP2/QEP2/IOPA4 ; 74377:94|33 ; A2 ;
; N/A ; None ; 13.000 ns ; CAP2/QEP2/IOPA4 ; 74377:94|33 ; A15 ;
; N/A ; None ; 13.000 ns ; CAP2/QEP2/IOPA4 ; 74377:94|33 ; A3 ;
; N/A ; None ; 13.000 ns ; CAP2/QEP2/IOPA4 ; 74377:94|33 ; A1 ;
; N/A ; None ; 13.000 ns ; CAP2/QEP2/IOPA4 ; 74377:94|33 ; A0 ;
; N/A ; None ; 13.000 ns ; CAP3/IOPA5 ; 74377:94|34 ; /IOS ;
; N/A ; None ; 13.000 ns ; CAP3/IOPA5 ; 74377:94|34 ; A2 ;
; N/A ; None ; 13.000 ns ; CAP3/IOPA5 ; 74377:94|34 ; A15 ;
; N/A ; None ; 13.000 ns ; CAP3/IOPA5 ; 74377:94|34 ; A3 ;
; N/A ; None ; 13.000 ns ; CAP3/IOPA5 ; 74377:94|34 ; A1 ;
; N/A ; None ; 13.000 ns ; CAP3/IOPA5 ; 74377:94|34 ; A0 ;
; N/A ; None ; 13.000 ns ; CAP4/QEP3/IOPE7 ; 74377:94|35 ; /IOS ;
; N/A ; None ; 13.000 ns ; CAP4/QEP3/IOPE7 ; 74377:94|35 ; A2 ;
; N/A ; None ; 13.000 ns ; CAP4/QEP3/IOPE7 ; 74377:94|35 ; A15 ;
; N/A ; None ; 13.000 ns ; CAP4/QEP3/IOPE7 ; 74377:94|35 ; A3 ;
; N/A ; None ; 13.000 ns ; CAP4/QEP3/IOPE7 ; 74377:94|35 ; A1 ;
; N/A ; None ; 13.000 ns ; CAP4/QEP3/IOPE7 ; 74377:94|35 ; A0 ;
; N/A ; None ; 12.000 ns ; RD[7] ; 74273:69|12 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[7] ; 74273:69|12 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[7] ; 74273:69|12 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[7] ; 74273:69|12 ; A3 ;
; N/A ; None ; 12.000 ns ; RD[6] ; 74273:69|13 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[6] ; 74273:69|13 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[6] ; 74273:69|13 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[6] ; 74273:69|13 ; A3 ;
; N/A ; None ; 12.000 ns ; RD[5] ; 74273:69|14 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[5] ; 74273:69|14 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[5] ; 74273:69|14 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[5] ; 74273:69|14 ; A3 ;
; N/A ; None ; 12.000 ns ; RD[4] ; 74273:69|15 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[4] ; 74273:69|15 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[4] ; 74273:69|15 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[4] ; 74273:69|15 ; A3 ;
; N/A ; None ; 12.000 ns ; RD[3] ; 74273:69|16 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[3] ; 74273:69|16 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[3] ; 74273:69|16 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[3] ; 74273:69|16 ; A3 ;
; N/A ; None ; 12.000 ns ; RD[2] ; 74273:69|17 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[2] ; 74273:69|17 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[2] ; 74273:69|17 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[2] ; 74273:69|17 ; A3 ;
; N/A ; None ; 12.000 ns ; RD[1] ; 74273:69|18 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[1] ; 74273:69|18 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[1] ; 74273:69|18 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[1] ; 74273:69|18 ; A3 ;
; N/A ; None ; 12.000 ns ; RD[0] ; 74273:69|19 ; /IOS ;
; N/A ; None ; 12.000 ns ; RD[0] ; 74273:69|19 ; A2 ;
; N/A ; None ; 12.000 ns ; RD[0] ; 74273:69|19 ; A15 ;
; N/A ; None ; 12.000 ns ; RD[0] ; 74273:69|19 ; A3 ;
+---------------+-------------+-----------+-----------------+-------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Dec 28 19:27:19 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cpld4gdf00 -c cpld4gdf00
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "A0" is an undefined clock
Info: Assuming node "A1" is an undefined clock
Info: Assuming node "A3" is an undefined clock
Info: Assuming node "A15" is an undefined clock
Info: Assuming node "A2" is an undefined clock
Info: Assuming node "/IOS" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "u11:109|u1:94|LEDS~29" as buffer
Info: Detected gated clock "u11:109|u1:94|LCD~4" as buffer
Info: No valid register-to-register data paths exist for clock "A0"
Info: No valid register-to-register data paths exist for clock "A1"
Info: No valid register-to-register data paths exist for clock "A3"
Info: No valid register-to-register data paths exist for clock "A15"
Info: No valid register-to-register data paths exist for clock "A2"
Info: No valid register-to-register data paths exist for clock "/IOS"
Info: tsu for register "74273:69|12" (data pin = "RD[7]", clock pin = "/IOS") is -4.000 ns
Info: + Longest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_132; Fanout = 1; PIN Node = 'RD[7]'
Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IO123; Fanout = 1; COMB Node = 'RD~0'
Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC92; Fanout = 1; REG Node = '74273:69|12'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro setup delay of destination is 4.000 ns
Info: - Shortest clock path from clock "/IOS" to destination register is 18.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 6; CLK Node = '/IOS'
Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP81; Fanout = 8; COMB Node = 'u11:109|u1:94|LEDS~29'
Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC92; Fanout = 1; REG Node = '74273:69|12'
Info: Total cell delay = 16.000 ns ( 88.89 % )
Info: Total interconnect delay = 2.000 ns ( 11.11 % )
Info: tco from clock "/IOS" to destination pin "LC/D" through register "74377:94|32" is 24.000 ns
Info: + Longest clock path from clock "/IOS" to source register is 19.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 6; CLK Node = '/IOS'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC51; Fanout = 12; COMB Node = 'u11:109|u1:94|LCD~4'
Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94|32'
Info: Total cell delay = 15.000 ns ( 78.95 % )
Info: Total interconnect delay = 4.000 ns ( 21.05 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94|32'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'LC/D'
Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Longest tpd from source pin "A14" to destination pin "UD0" is 31.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_16; Fanout = 1; PIN Node = 'A14'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC109; Fanout = 2; COMB Node = 'u11:109|u1:94|UCS~6'
Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC59; Fanout = 8; COMB Node = 'u11:109|u1:94|UCS~9'
Info: 4: + IC(2.000 ns) + CELL(9.000 ns) = 31.000 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'UD0'
Info: Total cell delay = 25.000 ns ( 80.65 % )
Info: Total interconnect delay = 6.000 ns ( 19.35 % )
Info: th for register "74377:94|32" (data pin = "CAP1/QEP1/IOPA3", clock pin = "/IOS") is 13.000 ns
Info: + Longest clock path from clock "/IOS" to destination register is 19.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 6; CLK Node = '/IOS'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC51; Fanout = 12; COMB Node = 'u11:109|u1:94|LCD~4'
Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94|32'
Info: Total cell delay = 15.000 ns ( 78.95 % )
Info: Total interconnect delay = 4.000 ns ( 21.05 % )
Info: + Micro hold delay of destination is 4.000 ns
Info: - Shortest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_27; Fanout = 1; PIN Node = 'CAP1/QEP1/IOPA3'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94|32'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Wed Dec 28 19:27:22 2005
Info: Elapsed time: 00:00:04
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