d4_16.rpt
来自「此文件是对xilinx95144器件编的程序」· RPT 代码 · 共 626 行 · 第 1/3 页
RPT
626 行
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 36 I/O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<0> XXXXXX.................................. 6 6
cs_out<5> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
cs_out<10> 1 0 0 4 FB4_2 STD 89 I/O O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 91 I/O
(unused) 0 0 0 5 FB4_6 92 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 93 I/O
(unused) 0 0 0 5 FB4_9 94 I/O
(unused) 0 0 0 5 FB4_10 (b)
cs_out<15> 1 0 0 4 FB4_11 STD 95 I/O O
(unused) 0 0 0 5 FB4_12 96 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 97 I/O I
(unused) 0 0 0 5 FB4_15 98 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 99 I/O I
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<10> XXXXXX.................................. 6 6
cs_out<15> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
cs_out<11> 1 0 0 4 FB5_2 STD 37 I/O O
(unused) 0 0 0 5 FB5_3 (b)
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 38 I/O
(unused) 0 0 0 5 FB5_6 39 I/O
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 41 I/O
(unused) 0 0 0 5 FB5_9 42 I/O
(unused) 0 0 0 5 FB5_10 (b)
cs_out<6> 1 0 0 4 FB5_11 STD 43 I/O O
(unused) 0 0 0 5 FB5_12 44 I/O
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 45 I/O
(unused) 0 0 0 5 FB5_15 48 I/O
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 51 I/O
(unused) 0 0 0 5 FB5_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<11> XXXXXX.................................. 6 6
cs_out<6> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
cs_out<12> 1 0 0 4 FB6_2 STD 76 I/O O
(unused) 0 0 0 5 FB6_3 (b)
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 78 I/O
(unused) 0 0 0 5 FB6_6 79 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 80 I/O
(unused) 0 0 0 5 FB6_9 81 I/O
(unused) 0 0 0 5 FB6_10 (b)
cs_out<1> 1 0 0 4 FB6_11 STD 82 I/O O
(unused) 0 0 0 5 FB6_12 83 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 84 I/O
(unused) 0 0 0 5 FB6_15 87 I/O
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 88 I/O
(unused) 0 0 0 5 FB6_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<12> XXXXXX.................................. 6 6
cs_out<1> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB7_1 (b)
cs_out<13> 1 0 0 4 FB7_2 STD 52 I/O O
(unused) 0 0 0 5 FB7_3 (b)
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 54 I/O
(unused) 0 0 0 5 FB7_6 55 I/O
(unused) 0 0 0 5 FB7_7 (b)
(unused) 0 0 0 5 FB7_8 56 I/O
(unused) 0 0 0 5 FB7_9 57 I/O
(unused) 0 0 0 5 FB7_10 (b)
cs_out<7> 1 0 0 4 FB7_11 STD 58 I/O O
(unused) 0 0 0 5 FB7_12 60 I/O
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 61 I/O
(unused) 0 0 0 5 FB7_15 62 I/O
(unused) 0 0 0 5 FB7_16 (b)
(unused) 0 0 0 5 FB7_17 63 I/O
(unused) 0 0 0 5 FB7_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<13> XXXXXX.................................. 6 6
cs_out<7> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
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