__projnav.log

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Total memory usage is 54092 kilobytesError: XST failedReason: Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.ERROR:HDLParsers:164 - D:/郑玉静/信箱/tba_2470/regd1.vhd Line 26. parse error, unexpected END, expecting SEMICOLONERROR:HDLParsers:164 - D:/郑玉静/信箱/tba_2470/regd1.vhd Line 29. parse error, unexpected PROCESS, expecting IF--> Total memory usage is 54092 kilobytesError: XST failedReason: Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.Entity <regd1> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <regd1> (Architecture <behavioral>).Entity <regd1> analyzed. Unit <regd1> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <regd1>.    Related source file is D:/郑玉静/信箱/tba_2470/regd1.vhd.WARNING:Xst:737 - Found 1-bit latch for signal <dout>.WARNING:Xst:737 - Found 1-bit latch for signal <ledd_1>.    Found 1 1-bit 2-to-1 multiplexers.WARNING:Xst:1306 - Output <ledd<3>> is never assigned.WARNING:Xst:1306 - Output <ledd<2>> is never assigned.Unit <regd1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Latches                          : 2  1-bit latch                      : 2# Multiplexers                     : 1  2-to-1 multiplexer               : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <regd1> ...Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.Entity <regd1> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <regd1> (Architecture <behavioral>).INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.Entity <regd1> analyzed. Unit <regd1> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <regd1>.    Related source file is D:/郑玉静/信箱/tba_2470/regd1.vhd.    Found 1-bit register for signal <dout>.WARNING:Xst:1306 - Output <ledd<3>> is never assigned.WARNING:Xst:1306 - Output <ledd<2>> is never assigned.    Summary:	inferred   1 D-type flip-flop(s).Unit <regd1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 1  1-bit register                   : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <regd1> ...Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.Entity <regd1> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <regd1> (Architecture <behavioral>).INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <ledd<0>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.Entity <regd1> analyzed. Unit <regd1> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <regd1>.    Related source file is D:/郑玉静/信箱/tba_2470/regd1.vhd.    Found 1-bit register for signal <dout>.WARNING:Xst:1306 - Output <ledd<3>> is never assigned.WARNING:Xst:1306 - Output <ledd<2>> is never assigned.    Summary:	inferred   1 D-type flip-flop(s).Unit <regd1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 1  1-bit register                   : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedWARNING:Xst:528 - Multi-source in Unit <regd1> on signal <cs> not replaced by logicSignal is stuck at GNDWARNING:Xst:528 - Multi-source in Unit <regd1> on signal <ledd<1>> not replaced by logicSignal is stuck at GNDERROR:Xst:415 - Synthesis failedCPU : 0.11 / 0.33 s | Elapsed : 0.00 / 1.00 s --> Total memory usage is 55116 kilobytesCompleted process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.Entity <regd1> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <regd1> (Architecture <behavioral>).INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <ledd<0>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.Entity <regd1> analyzed. Unit <regd1> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <regd1>.    Related source file is D:/郑玉静/信箱/tba_2470/regd1.vhd.    Found 1-bit register for signal <dout>.WARNING:Xst:1306 - Output <ledd<3>> is never assigned.WARNING:Xst:1306 - Output <ledd<2>> is never assigned.    Summary:	inferred   1 D-type flip-flop(s).Unit <regd1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 1  1-bit register                   : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedWARNING:Xst:528 - Multi-source in Unit <regd1> on signal <cs> not replaced by logicSignal is stuck at GNDWARNING:Xst:528 - Multi-source in Unit <regd1> on signal <ledd<1>> not replaced by logicSignal is stuck at GNDERROR:Xst:415 - Synthesis failedCPU : 0.11 / 0.33 s | Elapsed : 0.00 / 0.00 s --> Total memory usage is 55116 kilobytesCompleted process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator A
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