__projnav.log

来自「此文件是对xilinx95144器件编的程序」· LOG 代码 · 共 1,983 行 · 第 1/5 页

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Synthesizing Unit <tba_2472>.    Related source file is D:/郑玉静/信箱/tba_2470/tba-2472.vhd.WARNING:Xst:652 - Inout <p0<7>> is used but never assigned.WARNING:Xst:652 - Inout <p0<6>> is used but never assigned.WARNING:Xst:646 - Signal <cs_reg<15>> is assigned but never used.WARNING:Xst:646 - Signal <cs_reg<14>> is assigned but never used.WARNING:Xst:646 - Signal <cs_reg<13>> is assigned but never used.Unit <tba_2472> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 14  3-bit register                   : 1  4-bit register                   : 2  1-bit register                   : 9  2-bit register                   : 1  8-bit register                   : 1# Latches                          : 10  1-bit latch                      : 9  6-bit latch                      : 1# Multiplexers                     : 5  2-to-1 multiplexer               : 5# Tristates                        : 1  4-bit tristate buffer            : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedWARNING:Xst:528 - Multi-source in Unit <tba_2472> on signal <p0<0>> not replaced by logicSources are: regd1_2:dout<0>, regd1_1:dout<0>, regd1_6:dout<0>, regd1_4:dout<0>, regd1_3:dout<0>WARNING:Xst:528 - Multi-source in Unit <tba_2472> on signal <ledd<3>> not replaced by logicSources are: regd1_4:ledd<3>, regd1_6:ledd<3>, regd1_1:ledd<3>, regd1_2:ledd<3>, regd1_3:ledd<3>WARNING:Xst:528 - Multi-source in Unit <tba_2472> on signal <ledd<2>> not replaced by logicSources are: regd1_4:ledd<2>, regd1_6:ledd<2>, regd1_1:ledd<2>, regd1_2:ledd<2>, regd1_3:ledd<2>WARNING:Xst:528 - Multi-source in Unit <tba_2472> on signal <ledd<1>> not replaced by logicSources are: regd1_4:ledd<1>, regd1_6:ledd<1>, regd1_1:ledd<1>, regd1_2:ledd<1>, regd1_3:ledd<1>WARNING:Xst:528 - Multi-source in Unit <tba_2472> on signal <ledd<0>> not replaced by logicSources are: regd1_4:ledd<0>, regd1_6:ledd<0>, regd1_1:ledd<0>, regd1_2:ledd<0>, regd1_3:ledd<0>ERROR:Xst:415 - Synthesis failedCPU : 0.97 / 1.19 s | Elapsed : 1.00 / 1.00 s --> Total memory usage is 59212 kilobytesCompleted process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    tba-2472.vhd
Scanning    tba-2472.vhd
Writing tba-2472.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    tba-2472.vhd
Scanning    tba-2472.vhd
Writing tba-2472.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    tba-2472.vhd
Scanning    tba-2472.vhd
Writing tba-2472.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    tba-2472.vhd
Scanning    tba-2472.vhd
Writing tba-2472.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/d4_16.vhd in Library work.Architecture behavioral of Entity d4_16 is up to date.Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg.vhd in Library work.Architecture behavioral of Entity reg is up to date.Compiling vhdl file D:/郑玉静/信箱/tba_2470/latch.vhd in Library work.Architecture behavioral of Entity latch is up to date.Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_4.vhd in Library work.Architecture behavioral of Entity reg2_4 is up to date.Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_3.vhd in Library work.Architecture behavioral of Entity reg2_3 is up to date.Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.Architecture behavioral of Entity regd is up to date.Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.ERROR:HDLParsers:800 - D:/郑玉静/信箱/tba_2470/regd1.vhd Line 24. Type of dout is incompatible with type of din.--> Total memory usage is 55116 kilobytesError: XST failedReason: Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.ERROR:HDLParsers:800 - D:/郑玉静/信箱/tba_2470/regd1.vhd Line 24. Type of dout is incompatible with type of din.--> Total memory usage is 54092 kilobytesError: XST failedReason: Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.Entity <regd1> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <regd1> (Architecture <behavioral>).Entity <regd1> analyzed. Unit <regd1> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <regd1>.    Related source file is D:/郑玉静/信箱/tba_2470/regd1.vhd.WARNING:Xst:737 - Found 1-bit latch for signal <ledd_1>.WARNING:Xst:737 - Found 1-bit latch for signal <dout>.    Found 1 1-bit 2-to-1 multiplexers.WARNING:Xst:1306 - Output <ledd<3>> is never assigned.WARNING:Xst:1306 - Output <ledd<2>> is never assigned.Unit <regd1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Latches                          : 2  1-bit latch                      : 2# Multiplexers                     : 1  2-to-1 multiplexer               : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <regd1> ...Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.Entity <regd1> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <regd1> (Architecture <behavioral>).INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd1> never changes during circuit operation. The register is replaced by logic.Entity <regd1> analyzed. Unit <regd1> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <regd1>.    Related source file is D:/郑玉静/信箱/tba_2470/regd1.vhd.WARNING:Xst:737 - Found 1-bit latch for signal <dout>.    Found 1 1-bit 2-to-1 multiplexers.WARNING:Xst:1306 - Output <ledd<3>> is never assigned.WARNING:Xst:1306 - Output <ledd<2>> is never assigned.Unit <regd1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Latches                          : 1  1-bit latch                      : 1# Multiplexers                     : 1  2-to-1 multiplexer               : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <regd1> ...Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd1.vhd
Scanning    regd1.vhd
Writing regd1.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd1.vhd in Library work.ERROR:HDLParsers:164 - D:/郑玉静/信箱/tba_2470/regd1.vhd Line 26. parse error, unexpected END, expecting SEMICOLONERROR:HDLParsers:164 - D:/郑玉静/信箱/tba_2470/regd1.vhd Line 29. parse error, unexpected PROCESS, expecting IF-->
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