__projnav.log

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-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <ledd<2>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
ERROR:Xst:827 - D:/郑玉静/信箱/tba_2470/regd.vhd line 18: Signal ledd<1> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 54092 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <ledd<2>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
Entity <regd> analyzed. Unit <regd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regd>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
    Found 1-bit register for signal <dout<0>>.
WARNING:Xst:1306 - Output <ledd<3>> is never assigned.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <regd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
  1-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <regd> ...

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <ledd<2>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
ERROR:Xst:827 - D:/郑玉静/信箱/tba_2470/regd.vhd line 18: Signal ledd<1> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 54092 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
Entity <regd> analyzed. Unit <regd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regd>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
WARNING:Xst:737 - Found 1-bit latch for signal <ledd_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <dout_0>.
    Found 1 1-bit 2-to-1 multiplexers.
WARNING:Xst:1306 - Output <ledd<3>> is never assigned.
WARNING:Xst:1306 - Output <ledd<2>> is never assigned.
Unit <regd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 2
  1-bit latch                      : 2
# Multiplexers                     : 1
  2-to-1 multiplexer               : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <regd> ...

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    tba-2472.vhd
Scanning    tba-2472.vhd
Writing tba-2472.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/d4_16.vhd in Library work.
Architecture behavioral of Entity d4_16 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg.vhd in Library work.
Architecture behavioral of Entity reg is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/latch.vhd in Library work.
Architecture behavioral of Entity latch is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_4.vhd in Library work.
Architecture behavioral of Entity reg2_4 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_3.vhd in Library work.
Architecture behavioral of Entity reg2_3 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Architecture behavioral of Entity regd is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/tba-2472.vhd in Library work.
Entity <tba_2472> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <tba_2472> (Architecture <behavioral>).
Entity <tba_2472> analyzed. Unit <tba_2472> generated.

Analyzing Entity <d4_16> (Architecture <behavioral>).
INFO:Xst:1561 - D:/郑玉静/信箱/tba_2470/d4_16.vhd line 37: Mux is complete : default of case is discarded
Entity <d4_16> analyzed. Unit <d4_16> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 1
Entity <reg> analyzed. Unit <reg> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 8
Entity <reg> analyzed. Unit <reg0> generated.

Analyzing generic Entity <latch> (Architecture <behavioral>).
	size = 4
Entity <latch> analyzed. Unit <latch> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 2
Entity <reg> analyzed. Unit <reg1> generated.

Analyzing Entity <reg2_4> (Architecture <behavioral>).
INFO:Xst:1561 - D:/郑玉静/信箱/tba_2470/reg2_4.vhd line 57: Mux is complete : default of case is discarded
Entity <reg2_4> analyzed. Unit <reg2_4> generated.

Analyzing Entity <reg2_3> (Architecture <behavioral>).
Entity <reg2_3> analyzed. Unit <reg2_3> generated.

Analyzing generic Entity <regd> (Architecture <behavioral>).
	size = 6
Entity <regd> analyzed. Unit <regd> generated.

Analyzing generic Entity <regd> (Architecture <behavioral>).
	size = 1
Entity <regd> analyzed. Unit <regd2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regd2>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
WARNING:Xst:737 - Found 1-bit latch for signal <ledd_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <dout_0>.
    Found 1 1-bit 2-to-1 multiplexers.
WARNING:Xst:1305 - Output <ledd<3>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<2>> is never assigned. Tied to value 0.
Unit <regd2> synthesized.


Synthesizing Unit <regd>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
WARNING:Xst:737 - Found 1-bit latch for signal <ledd_1>.
WARNING:Xst:737 - Found 6-bit latch for signal <dout>.
    Found 6 1-bit 2-to-1 multiplexers.
WARNING:Xst:1305 - Output <ledd<3>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<2>> is never assigned. Tied to value 0.
Unit <regd> synthesized.


Synthesizing Unit <reg2_3>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg2_3.vhd.
    Found 3-bit register for signal <dout>.
Unit <reg2_3> synthesized.


Synthesizing Unit <reg2_4>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg2_4.vhd.
    Found 4-bit register for signal <dout>.
Unit <reg2_4> synthesized.


Synthesizing Unit <reg1>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 2-bit register for signal <dout>.
Unit <reg1> synthesized.


Synthesizing Unit <latch>.
    Related source file is D:/郑玉静/信箱/tba_2470/latch.vhd.
    Found 4-bit tristate buffer for signal <dout>.
    Found 4-bit register for signal <Mtridata_dout> created at line 18.
    Summary:
	inferred   4 Tristate(s).
Unit <latch> synthesized.


Synthesizing Unit <reg0>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 8-bit register for signal <dout>.
Unit <reg0> synthesized.


Synthesizing Unit <reg>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 1-bit register for signal <dout<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <reg> synthesized.


Synthesizing Unit <d4_16>.
    Related source file is D:/郑玉静/信箱/tba_2470/d4_16.vhd.
Unit <d4_16> synthesized.