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Unit <reg2_3> synthesized.


Synthesizing Unit <reg2_4>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg2_4.vhd.
    Found 4-bit register for signal <dout>.
Unit <reg2_4> synthesized.


Synthesizing Unit <reg1>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 2-bit register for signal <dout>.
Unit <reg1> synthesized.


Synthesizing Unit <latch>.
    Related source file is D:/郑玉静/信箱/tba_2470/latch.vhd.
    Found 4-bit tristate buffer for signal <dout>.
    Found 4-bit register for signal <Mtridata_dout> created at line 18.
    Summary:
	inferred   4 Tristate(s).
Unit <latch> synthesized.


Synthesizing Unit <reg0>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 8-bit register for signal <dout>.
Unit <reg0> synthesized.


Synthesizing Unit <reg>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 1-bit register for signal <dout<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <reg> synthesized.


Synthesizing Unit <d4_16>.
    Related source file is D:/郑玉静/信箱/tba_2470/d4_16.vhd.
Unit <d4_16> synthesized.


Synthesizing Unit <tba_2472>.
    Related source file is D:/郑玉静/信箱/tba_2470/tba-2472.vhd.
WARNING:Xst:652 - Inout <p0<7>> is used but never assigned.
WARNING:Xst:652 - Inout <p0<6>> is used but never assigned.
WARNING:Xst:646 - Signal <cs_reg<15>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_reg<14>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_reg<13>> is assigned but never used.
Unit <tba_2472> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 14
  3-bit register                   : 1
  4-bit register                   : 2
  1-bit register                   : 9
  2-bit register                   : 1
  8-bit register                   : 1
# Tristates                        : 6
  1-bit tristate buffer            : 4
  4-bit tristate buffer            : 1
  6-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted
WARNING:Xst:1348 - Unit regd2 is merged (output interface has tristates)
WARNING:Xst:1348 - Unit regd is merged (output interface has tristates)

Optimizing unit <tba_2472> ...

Optimizing unit <d4_16> ...

Optimizing unit <reg> ...

Optimizing unit <reg0> ...

Optimizing unit <latch> ...
  implementation constraint: iob	 : Mtridata_dout<1>
  implementation constraint: KEEP	 : Mtridata_dout<1>
  implementation constraint: iob	 : Mtridata_dout<0>
  implementation constraint: KEEP	 : Mtridata_dout<0>
  implementation constraint: iob	 : Mtridata_dout<3>
  implementation constraint: KEEP	 : Mtridata_dout<3>
  implementation constraint: iob	 : Mtridata_dout<2>
  implementation constraint: KEEP	 : Mtridata_dout<2>

Optimizing unit <reg1> ...

Optimizing unit <reg2_4> ...

Optimizing unit <reg2_3> ...

Completed process "Synthesize".



Project Navigator Auto-Make Log File
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Started process "Translate".

Release 5.2.03i - ngdbuild F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc ttb2470.ucf -p xc9500 tba_2472.ngc
tba_2472.ngd 

Reading NGO file "D:/郑玉静/信箱/tba_2470/tba_2472.ngc" ...
Reading component libraries for design expansion...
INFO:NgdBuild:782 - output buffer 'check_2_obuf' driving design level port
   'check<2>' is being pushed into module 'reg3_1' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'check_1_obuf' driving design level port
   'check<1>' is being pushed into module 'reg3_1' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'check_0_obuf' driving design level port
   'check<0>' is being pushed into module 'reg3_1' to enable I/O register usage.

Annotating constraints to design from file "ttb2470.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "tba_2472.ngd" ...

Writing NGDBUILD log file "tba_2472.bld"...

NGDBUILD done.

Completed process "Translate".



Project Navigator Auto-Make Log File
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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <ledd<2>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
Entity <regd> analyzed. Unit <regd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regd>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
    Found 1-bit register for signal <dout<0>>.
WARNING:Xst:1306 - Output <ledd<3>> is never assigned.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <regd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
  1-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <regd> ...

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <ledd<1>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <ledd<2>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
Entity <regd> analyzed. Unit <regd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regd>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
    Found 1-bit register for signal <dout<0>>.
WARNING:Xst:1306 - Output <ledd<3>> is never assigned.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <regd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
  1-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <regd> ...

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
ERROR:Xst:827 - D:/郑玉静/信箱/tba_2470/regd.vhd line 18: Signal ledd<1> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 54092 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <regd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <ledd<2>> in unit <regd> never changes during circuit operation. The register is replaced by logic.
ERROR:Xst:827 - D:/郑玉静/信箱/tba_2470/regd.vhd line 18: Signal ledd<1> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 54092 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".