__projnav.log

来自「此文件是对xilinx95144器件编的程序」· LOG 代码 · 共 1,983 行 · 第 1/5 页

o-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/d4_16.vhd in Library work.
Architecture behavioral of Entity d4_16 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg.vhd in Library work.
Architecture behavioral of Entity reg is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/latch.vhd in Library work.
Architecture behavioral of Entity latch is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_4.vhd in Library work.
Architecture behavioral of Entity reg2_4 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_3.vhd in Library work.
Architecture behavioral of Entity reg2_3 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Architecture behavioral of Entity regd is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/tba-2472.vhd in Library work.
Architecture behavioral of Entity tba_2472 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <tba_2472> (Architecture <behavioral>).
Entity <tba_2472> analyzed. Unit <tba_2472> generated.

Analyzing Entity <d4_16> (Architecture <behavioral>).
INFO:Xst:1561 - D:/郑玉静/信箱/tba_2470/d4_16.vhd line 37: Mux is complete : default of case is discarded
Entity <d4_16> analyzed. Unit <d4_16> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 1
Entity <reg> analyzed. Unit <reg> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 8
Entity <reg> analyzed. Unit <reg0> generated.

Analyzing generic Entity <latch> (Architecture <behavioral>).
	size = 4
Entity <latch> analyzed. Unit <latch> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 2
Entity <reg> analyzed. Unit <reg1> generated.

Analyzing Entity <reg2_4> (Architecture <behavioral>).
INFO:Xst:1561 - D:/郑玉静/信箱/tba_2470/reg2_4.vhd line 57: Mux is complete : default of case is discarded
Entity <reg2_4> analyzed. Unit <reg2_4> generated.

Analyzing Entity <reg2_3> (Architecture <behavioral>).
Entity <reg2_3> analyzed. Unit <reg2_3> generated.

Analyzing generic Entity <regd> (Architecture <behavioral>).
	size = 6
Entity <regd> analyzed. Unit <regd> generated.

Analyzing generic Entity <regd> (Architecture <behavioral>).
	size = 1
Entity <regd> analyzed. Unit <regd2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regd2>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
    Found 1-bit tristate buffer for signal <dout<0>>.
    Summary:
	inferred   1 Tristate(s).
Unit <regd2> synthesized.


Synthesizing Unit <regd>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
    Found 6-bit tristate buffer for signal <dout>.
    Summary:
	inferred   6 Tristate(s).
Unit <regd> synthesized.


Synthesizing Unit <reg2_3>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg2_3.vhd.
    Found 3-bit register for signal <dout>.
Unit <reg2_3> synthesized.


Synthesizing Unit <reg2_4>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg2_4.vhd.
    Found 4-bit register for signal <dout>.
Unit <reg2_4> synthesized.


Synthesizing Unit <reg1>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 2-bit register for signal <dout>.
Unit <reg1> synthesized.


Synthesizing Unit <latch>.
    Related source file is D:/郑玉静/信箱/tba_2470/latch.vhd.
    Found 4-bit tristate buffer for signal <dout>.
    Found 4-bit register for signal <Mtridata_dout> created at line 18.
    Summary:
	inferred   4 Tristate(s).
Unit <latch> synthesized.


Synthesizing Unit <reg0>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 8-bit register for signal <dout>.
Unit <reg0> synthesized.


Synthesizing Unit <reg>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg.vhd.
    Found 1-bit register for signal <dout<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <reg> synthesized.


Synthesizing Unit <d4_16>.
    Related source file is D:/郑玉静/信箱/tba_2470/d4_16.vhd.
Unit <d4_16> synthesized.


Synthesizing Unit <tba_2472>.
    Related source file is D:/郑玉静/信箱/tba_2470/tba-2472.vhd.
WARNING:Xst:1306 - Output <ledd<3>> is never assigned.
WARNING:Xst:1306 - Output <ledd<2>> is never assigned.
WARNING:Xst:1306 - Output <ledd<1>> is never assigned.
WARNING:Xst:1306 - Output <ledd<0>> is never assigned.
WARNING:Xst:652 - Inout <p0<7>> is used but never assigned.
WARNING:Xst:652 - Inout <p0<6>> is used but never assigned.
WARNING:Xst:646 - Signal <cs_reg<15>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_reg<14>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_reg<13>> is assigned but never used.
Unit <tba_2472> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 14
  3-bit register                   : 1
  4-bit register                   : 2
  1-bit register                   : 9
  2-bit register                   : 1
  8-bit register                   : 1
# Tristates                        : 6
  1-bit tristate buffer            : 4
  4-bit tristate buffer            : 1
  6-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted
WARNING:Xst:1348 - Unit regd2 is merged (output interface has tristates)
WARNING:Xst:1348 - Unit regd is merged (output interface has tristates)

Optimizing unit <tba_2472> ...

Optimizing unit <d4_16> ...

Optimizing unit <reg> ...

Optimizing unit <reg0> ...

Optimizing unit <latch> ...
  implementation constraint: iob	 : Mtridata_dout<1>
  implementation constraint: KEEP	 : Mtridata_dout<1>
  implementation constraint: iob	 : Mtridata_dout<0>
  implementation constraint: KEEP	 : Mtridata_dout<0>
  implementation constraint: iob	 : Mtridata_dout<3>
  implementation constraint: KEEP	 : Mtridata_dout<3>
  implementation constraint: iob	 : Mtridata_dout<2>
  implementation constraint: KEEP	 : Mtridata_dout<2>

Optimizing unit <reg1> ...

Optimizing unit <reg2_4> ...

Optimizing unit <reg2_3> ...

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    tba-2472.vhd
Scanning    tba-2472.vhd
Writing tba-2472.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/d4_16.vhd in Library work.
Architecture behavioral of Entity d4_16 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg.vhd in Library work.
Architecture behavioral of Entity reg is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/latch.vhd in Library work.
Architecture behavioral of Entity latch is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_4.vhd in Library work.
Architecture behavioral of Entity reg2_4 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_3.vhd in Library work.
Architecture behavioral of Entity reg2_3 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
ERROR:HDLParsers:3312 - D:/郑玉静/信箱/tba_2470/regd.vhd Line 10. Undefined symbol 'ledd'.
ERROR:HDLParsers:1209 - D:/郑玉静/信箱/tba_2470/regd.vhd Line 10. ledd: Undefined symbol (last report in this block)
ERROR:HDLParsers:507 - D:/郑玉静/信箱/tba_2470/regd.vhd Line 9. ) is not a correct resolution function name
ERROR:HDLParsers:164 - D:/郑玉静/信箱/tba_2470/regd.vhd Line 10. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR
--> 

Total memory usage is 55116 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    regd.vhd
Scanning    regd.vhd
Writing regd.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    tba-2472.vhd
Scanning    tba-2472.vhd
Writing tba-2472.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/郑玉静/信箱/tba_2470/d4_16.vhd in Library work.
Architecture behavioral of Entity d4_16 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg.vhd in Library work.
Architecture behavioral of Entity reg is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/latch.vhd in Library work.
Architecture behavioral of Entity latch is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_4.vhd in Library work.
Architecture behavioral of Entity reg2_4 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/reg2_3.vhd in Library work.
Architecture behavioral of Entity reg2_3 is up to date.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/regd.vhd in Library work.
Entity <regd> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/郑玉静/信箱/tba_2470/tba-2472.vhd in Library work.
Entity <tba_2472> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <tba_2472> (Architecture <behavioral>).
Entity <tba_2472> analyzed. Unit <tba_2472> generated.

Analyzing Entity <d4_16> (Architecture <behavioral>).
INFO:Xst:1561 - D:/郑玉静/信箱/tba_2470/d4_16.vhd line 37: Mux is complete : default of case is discarded
Entity <d4_16> analyzed. Unit <d4_16> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 1
Entity <reg> analyzed. Unit <reg> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 8
Entity <reg> analyzed. Unit <reg0> generated.

Analyzing generic Entity <latch> (Architecture <behavioral>).
	size = 4
Entity <latch> analyzed. Unit <latch> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 2
Entity <reg> analyzed. Unit <reg1> generated.

Analyzing Entity <reg2_4> (Architecture <behavioral>).
INFO:Xst:1561 - D:/郑玉静/信箱/tba_2470/reg2_4.vhd line 57: Mux is complete : default of case is discarded
Entity <reg2_4> analyzed. Unit <reg2_4> generated.

Analyzing Entity <reg2_3> (Architecture <behavioral>).
Entity <reg2_3> analyzed. Unit <reg2_3> generated.

Analyzing generic Entity <regd> (Architecture <behavioral>).
	size = 6
Entity <regd> analyzed. Unit <regd> generated.

Analyzing generic Entity <regd> (Architecture <behavioral>).
	size = 1
Entity <regd> analyzed. Unit <regd2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regd2>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
    Found 1-bit tristate buffer for signal <dout<0>>.
WARNING:Xst:1305 - Output <ledd<3>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<2>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<1>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<0>> is never assigned. Tied to value 0.
    Summary:
	inferred   1 Tristate(s).
Unit <regd2> synthesized.


Synthesizing Unit <regd>.
    Related source file is D:/郑玉静/信箱/tba_2470/regd.vhd.
    Found 6-bit tristate buffer for signal <dout>.
WARNING:Xst:1305 - Output <ledd<3>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<2>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<1>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <ledd<0>> is never assigned. Tied to value 0.
    Summary:
	inferred   6 Tristate(s).
Unit <regd> synthesized.


Synthesizing Unit <reg2_3>.
    Related source file is D:/郑玉静/信箱/tba_2470/reg2_3.vhd.
    Found 3-bit register for signal <dout>.