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📄 tba_2472.mfd

📁 此文件是对xilinx95144器件编的程序
💻 MFD
📖 第 1 页 / 共 2 页
字号:
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12 

MACROCELL | 4 | 4 | pa_c_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 4 | 4
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | pa_c_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 4 | 4
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 6 | 
   pa_c.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) & 
	!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & !(pa_c_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & pa_c_obuf.FBK.LFBK;
   pa_c.CLK = !(wr);
   pa_c.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 4 | play_s_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 6 | 4
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | play_s_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 4
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   play_s.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	!(inter_add<1>) & inter_add<2> & !(inter_add<3>) & 
	!(play_s_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	!(inter_add<1>) & inter_add<2> & !(inter_add<3>) & 
	play_s_obuf.FBK.LFBK;
   play_s.CLK = !(wr);
   play_s.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 1 | stop_s_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 6 | 1
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | stop_s_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 1
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   stop_s.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) & 
	inter_add<1> & inter_add<2> & !(inter_add<3>) & 
	!(stop_s_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	inter_add<1> & inter_add<2> & !(inter_add<3>) & 
	stop_s_obuf.FBK.LFBK;
   stop_s.CLK = !(wr);
   stop_s.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 16 | updown_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 6 | 16
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | updown_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 16
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   updown.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	inter_add<1> & !(inter_add<2>) & !(inter_add<3>) & 
	!(updown_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	inter_add<1> & !(inter_add<2>) & !(inter_add<3>) & 
	updown_obuf.FBK.LFBK;
   updown.CLK = !(wr);
   updown.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 17 | inter_add<0>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 37 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 6 | 14 | 6 | 10 | 6 | 8 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3 | 7 | 17
INPUTS | 3 | p0<0>.PIN  | ale  | cs
INPUTP | 3 | 18 | 2 | 6
EQ | 3 | 
   inter_add<0>.D = p0<0>.PIN;
   inter_add<0>.CLK = !(ale);
   inter_add<0>.OE = !(cs);

MACROCELL | 5 | 15 | inter_add<1>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 37 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 6 | 14 | 6 | 10 | 6 | 8 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3 | 7 | 17
INPUTS | 3 | p0<1>.PIN  | ale  | cs
INPUTP | 3 | 19 | 2 | 6
EQ | 3 | 
   inter_add<1>.D = p0<1>.PIN;
   inter_add<1>.CLK = !(ale);
   inter_add<1>.OE = !(cs);

MACROCELL | 5 | 12 | inter_add<2>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 37 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 6 | 14 | 6 | 10 | 6 | 8 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3 | 7 | 17
INPUTS | 3 | p0<2>.PIN  | ale  | cs
INPUTP | 3 | 21 | 2 | 6
EQ | 3 | 
   inter_add<2>.D = p0<2>.PIN;
   inter_add<2>.CLK = !(ale);
   inter_add<2>.OE = !(cs);

MACROCELL | 5 | 9 | inter_add<3>
ATTRIBUTES | 8521504 | 0
OUTPUTMC | 37 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 6 | 14 | 6 | 10 | 6 | 8 | 0 | 1 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3
INPUTS | 3 | p0<3>.PIN  | ale  | cs
INPUTP | 3 | 22 | 2 | 6
EQ | 3 | 
   inter_add<3>.D = p0<3>.PIN;
   inter_add<3>.CLK = !(ale);
   inter_add<3>.OE = !(cs);

MACROCELL | 6 | 14 | reg3_1/dout<0>
ATTRIBUTES | 8786722 | 0
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 5 | 6 | 159 | 18 | 19 | 29
EQ | 4 | 
   !check<0>.D = !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	!(p0<1>.PIN) & !(inter_add<1>) & inter_add<2> & inter_add<3>;
   check<0>.CLK = !(wr);
   check<0>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 10 | reg3_1/dout<1>
ATTRIBUTES | 8786722 | 0
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 5 | 6 | 159 | 18 | 19 | 29
EQ | 4 | 
   !check<1>.D = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) & 
	!(p0<1>.PIN) & !(inter_add<1>) & inter_add<2> & inter_add<3>;
   check<1>.CLK = !(wr);
   check<1>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 8 | reg3_1/dout<2>
ATTRIBUTES | 8786722 | 0
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 5 | 6 | 159 | 18 | 19 | 29
EQ | 4 | 
   !check<2>.D = !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	p0<1>.PIN & !(inter_add<1>) & inter_add<2> & inter_add<3>;
   check<2>.CLK = !(wr);
   check<2>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 0 | 1 | p0_0_iobufe$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 6 | p0_0_iobufe  | cs  | reset  | inter_add<3>  | rd  | $OpTx$FX_DC$11
INPUTMC | 2 | 5 | 9 | 7 | 17
INPUTP | 3 | 6 | 159 | 30
EQ | 3 | 
   p0<0> = p0_0_iobufe;
   p0<0>.OE = !(cs) & !(reset) & !(inter_add<3>) & !(rd) & 
	$OpTx$FX_DC$11;

MACROCELL | 0 | 2 | speed_1_ibuf$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 8 | speed<1>  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 72 | 6 | 159 | 30
EQ | 3 | 
   p0<1> = speed<1>;
   p0<1>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & !(rd);

MACROCELL | 0 | 4 | speed_2_ibuf$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 8 | speed<2>  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 69 | 6 | 159 | 30
EQ | 3 | 
   p0<2> = speed<2>;
   p0<2>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & !(rd);

MACROCELL | 0 | 5 | speed_3_ibuf$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 8 | speed<3>  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 68 | 6 | 159 | 30
EQ | 3 | 
   p0<3> = speed<3>;
   p0<3>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & !(rd);

MACROCELL | 0 | 7 | speed_4_ibuf$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 8 | speed<4>  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 64 | 6 | 159 | 30
EQ | 3 | 
   p0<4> = speed<4>;
   p0<4>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & !(rd);

MACROCELL | 0 | 8 | speed_5_ibuf$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 8 | speed<5>  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 63 | 6 | 159 | 30
EQ | 3 | 
   p0<5> = speed<5>;
   p0<5>.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & !(rd);

MACROCELL | 7 | 15 | p0_0_iobufe$WA0
ATTRIBUTES | 134912 | 0
INPUTS | 8 | playing  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 96 | 6 | 159 | 30
EQ | 3 | 
   p0_0_iobufe$WA0 = playing;
   p0_0_iobufe$WA0.OE = !(cs) & !(reset) & !(inter_add<0>) & !(inter_add<1>) & 
	!(inter_add<2>) & !(inter_add<3>) & !(rd);

MACROCELL | 7 | 12 | p0_0_iobufe$WA1
ATTRIBUTES | 134912 | 0
INPUTS | 8 | speed<0>  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 77 | 6 | 159 | 30
EQ | 3 | 
   p0_0_iobufe$WA1 = speed<0>;
   p0_0_iobufe$WA1.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	inter_add<2> & !(inter_add<3>) & !(rd);

MACROCELL | 7 | 9 | p0_0_iobufe$WA2
ATTRIBUTES | 134912 | 0
INPUTS | 8 | m_s_in  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 62 | 6 | 159 | 30
EQ | 3 | 
   p0_0_iobufe$WA2 = m_s_in;
   p0_0_iobufe$WA2.OE = !(cs) & !(reset) & inter_add<0> & inter_add<1> & 
	!(inter_add<2>) & !(inter_add<3>) & !(rd);

MACROCELL | 7 | 6 | p0_0_iobufe$WA3
ATTRIBUTES | 134912 | 0
INPUTS | 8 | radio  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 86 | 6 | 159 | 30
EQ | 3 | 
   p0_0_iobufe$WA3 = radio;
   p0_0_iobufe$WA3.OE = !(cs) & !(reset) & !(inter_add<0>) & inter_add<1> & 
	!(inter_add<2>) & !(inter_add<3>) & !(rd);

MACROCELL | 7 | 3 | p0_0_iobufe$WA4
ATTRIBUTES | 134912 | 0
INPUTS | 8 | nofile  | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | rd
INPUTMC | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
INPUTP | 4 | 95 | 6 | 159 | 30
EQ | 3 | 
   p0_0_iobufe$WA4 = nofile;
   p0_0_iobufe$WA4.OE = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & !(inter_add<3>) & !(rd);

MACROCELL | 3 | 7 | ledd_3_obuf
ATTRIBUTES | 396034 | 0
INPUTS | 0
EQ | 1 | 
   ledd<3> = Gnd;

MACROCELL | 3 | 5 | ledd_3_obuf$BUF0
ATTRIBUTES | 396034 | 0
INPUTS | 0
EQ | 1 | 
   ledd<2> = Gnd;

MACROCELL | 3 | 4 | ledd_3_obuf$BUF1
ATTRIBUTES | 396034 | 0
INPUTS | 0
EQ | 1 | 
   ledd<1> = Gnd;

MACROCELL | 3 | 1 | ledd_3_obuf$BUF2
ATTRIBUTES | 396034 | 0
INPUTS | 0
EQ | 1 | 
   ledd<0> = Gnd;

MACROCELL | 7 | 17 | $OpTx$FX_DC$11
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 0 | 1
INPUTS | 3 | inter_add<2>  | inter_add<0>  | inter_add<1>
INPUTMC | 3 | 5 | 12 | 5 | 17 | 5 | 15
EQ | 2 | 
   $OpTx$FX_DC$11 = !(inter_add<2>)
	# !(inter_add<0>) & inter_add<1>;

PIN | cs | 64 | 0 | N/A | 6 | 41 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 14 | 6 | 10 | 6 | 8 | 0 | 1 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3
PIN | reset | 65600 | 0 | N/A | 159 | 37 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 6 | 14 | 6 | 10 | 6 | 8 | 0 | 1 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3
PIN | wr | 64 | 0 | N/A | 29 | 26 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 1 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 7 | 7 | 5 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 6 | 14 | 6 | 10 | 6 | 8
PIN | p0<6> | 64 | 0 | N/A | 26 | 1 | 7 | 7
PIN | p0<7> | 64 | 0 | N/A | 28 | 1 | 7 | 5
PIN | ale | 64 | 0 | N/A | 2 | 4 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9
PIN | rd | 64 | 0 | N/A | 30 | 11 | 0 | 1 | 0 | 2 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 8 | 7 | 15 | 7 | 12 | 7 | 9 | 7 | 6 | 7 | 3
PIN | speed<1> | 64 | 0 | N/A | 72 | 1 | 0 | 2
PIN | speed<2> | 64 | 0 | N/A | 69 | 1 | 0 | 4
PIN | speed<3> | 64 | 0 | N/A | 68 | 1 | 0 | 5
PIN | speed<4> | 64 | 0 | N/A | 64 | 1 | 0 | 7
PIN | speed<5> | 64 | 0 | N/A | 63 | 1 | 0 | 8
PIN | playing | 64 | 0 | N/A | 96 | 1 | 7 | 15
PIN | speed<0> | 64 | 0 | N/A | 77 | 1 | 7 | 12
PIN | m_s_in | 64 | 0 | N/A | 62 | 1 | 7 | 9
PIN | radio | 64 | 0 | N/A | 86 | 1 | 7 | 6
PIN | nofile | 64 | 0 | N/A | 95 | 1 | 7 | 3
PIN | en485 | 536871040 | 0 | N/A | 145
PIN | lcd_c | 536871040 | 0 | N/A | 88
PIN | led1 | 536871040 | 0 | N/A | 139
PIN | led<2> | 536871040 | 0 | N/A | 138
PIN | led<3> | 536871040 | 0 | N/A | 135
PIN | led<4> | 536871040 | 0 | N/A | 134
PIN | led<5> | 536871040 | 0 | N/A | 133
PIN | load | 536871040 | 0 | N/A | 129
PIN | m_s_out | 536871040 | 0 | N/A | 60
PIN | outputh<8> | 536871040 | 0 | N/A | 102
PIN | outputh<9> | 536871040 | 0 | N/A | 101
PIN | outputl<0> | 536871040 | 0 | N/A | 116
PIN | outputl<1> | 536871040 | 0 | N/A | 115
PIN | outputl<2> | 536871040 | 0 | N/A | 113
PIN | outputl<3> | 536871040 | 0 | N/A | 111
PIN | outputl<4> | 536871040 | 0 | N/A | 108
PIN | outputl<5> | 536871040 | 0 | N/A | 106
PIN | outputl<6> | 536871040 | 0 | N/A | 104
PIN | outputl<7> | 536871040 | 0 | N/A | 103
PIN | pa_c | 536871040 | 0 | N/A | 59
PIN | play_s | 536871040 | 0 | N/A | 82
PIN | stop_s | 536871040 | 0 | N/A | 79
PIN | updown | 536871040 | 0 | N/A | 98
PIN | check<0> | 536871040 | 0 | N/A | 97
PIN | check<1> | 536871040 | 0 | N/A | 92
PIN | check<2> | 536871040 | 0 | N/A | 90
PIN | ledd<3> | 536871040 | 0 | N/A | 144
PIN | ledd<2> | 536871040 | 0 | N/A | 143
PIN | ledd<1> | 536871040 | 0 | N/A | 142
PIN | ledd<0> | 536871040 | 0 | N/A | 140
PIN | p0<0> | 536870976 | 0 | N/A | 18 | 19 | 3 | 8 | 6 | 7 | 5 | 16 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 5 | 8 | 4 | 5 | 7 | 4 | 7 | 16 | 4 | 4 | 6 | 4 | 6 | 1 | 6 | 16 | 5 | 17 | 6 | 14 | 6 | 10 | 6 | 8
PIN | p0<1> | 536870976 | 0 | N/A | 19 | 10 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 7 | 1 | 7 | 14 | 5 | 15 | 6 | 14 | 6 | 10 | 6 | 8
PIN | p0<2> | 536870976 | 0 | N/A | 21 | 6 | 5 | 14 | 5 | 13 | 5 | 11 | 5 | 10 | 7 | 13 | 5 | 12
PIN | p0<3> | 536870976 | 0 | N/A | 22 | 2 | 7 | 11 | 5 | 9
PIN | p0<4> | 536870976 | 0 | N/A | 23 | 1 | 7 | 10
PIN | p0<5> | 536870976 | 0 | N/A | 24 | 1 | 7 | 8
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