tba_2472.mfd

此文件是对xilinx95144器件编的程序

MDF Database:  version 1.0
MDF_INFO | tba_2472 | XC95144-7-PQ100
MACROCELL | 3 | 8 | en485_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 3 | 8
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | en485_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 3 | 8
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   en485.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) & 
	!(inter_add<1>) & !(inter_add<2>) & !(inter_add<3>) & 
	!(en485_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	!(inter_add<1>) & !(inter_add<2>) & !(inter_add<3>) & 
	en485_obuf.FBK.LFBK;
   en485.CLK = !(wr);
   en485.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 6 | 7 | lcd_c_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 6 | 7
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | lcd_c_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 6 | 7
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   lcd_c.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) & 
	!(inter_add<1>) & inter_add<2> & !(inter_add<3>) & 
	!(lcd_c_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	!(inter_add<1>) & inter_add<2> & !(inter_add<3>) & 
	lcd_c_obuf.FBK.LFBK;
   lcd_c.CLK = !(wr);
   lcd_c.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 16 | led1_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 5 | 16
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | led1_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 5 | 16
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 6 | 
   led1.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	!(inter_add<1>) & !(inter_add<2>) & !(inter_add<3>) & !(led1_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	!(inter_add<1>) & !(inter_add<2>) & !(inter_add<3>) & led1_obuf.FBK.LFBK;
   led1.CLK = !(wr);
   led1.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 14 | led_2_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 5 | 14
INPUTS | 11 | cs  | reset  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<2>.PIN  | p0<0>.PIN  | wr  | led_2_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 5 | 14
INPUTP | 6 | 6 | 159 | 19 | 21 | 18 | 29
EQ | 14 | 
   led<2>.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_2_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & p0<1>.PIN & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_2_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & inter_add<1> & 
	p0<2>.PIN & !(inter_add<2>) & inter_add<3> & 
	!(led_2_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	!(p0<1>.PIN) & inter_add<1> & !(p0<2>.PIN) & !(inter_add<2>) & 
	inter_add<3> & led_2_obuf.FBK.LFBK;
   led<2>.CLK = !(wr);
   led<2>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 13 | led_3_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 5 | 13
INPUTS | 11 | cs  | reset  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<2>.PIN  | p0<0>.PIN  | wr  | led_3_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 5 | 13
INPUTP | 6 | 6 | 159 | 19 | 21 | 18 | 29
EQ | 14 | 
   led<3>.T = !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_3_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & p0<1>.PIN & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_3_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & inter_add<1> & 
	p0<2>.PIN & !(inter_add<2>) & inter_add<3> & 
	!(led_3_obuf.FBK.LFBK)
	# !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	!(p0<1>.PIN) & inter_add<1> & !(p0<2>.PIN) & !(inter_add<2>) & 
	inter_add<3> & led_3_obuf.FBK.LFBK;
   led<3>.CLK = !(wr);
   led<3>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 11 | led_4_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 5 | 11
INPUTS | 11 | cs  | reset  | inter_add<0>  | inter_add<1>  | p0<2>.PIN  | inter_add<2>  | inter_add<3>  | p0<0>.PIN  | p0<1>.PIN  | wr  | led_4_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 5 | 11
INPUTP | 6 | 6 | 159 | 21 | 18 | 19 | 29
EQ | 14 | 
   led<4>.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_4_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(p0<1>.PIN) & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_4_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & inter_add<1> & 
	p0<2>.PIN & !(inter_add<2>) & inter_add<3> & 
	!(led_4_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	p0<1>.PIN & inter_add<1> & !(p0<2>.PIN) & !(inter_add<2>) & 
	inter_add<3> & led_4_obuf.FBK.LFBK;
   led<4>.CLK = !(wr);
   led<4>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 10 | led_5_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 5 | 10
INPUTS | 11 | cs  | reset  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<2>.PIN  | p0<0>.PIN  | wr  | led_5_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 5 | 10
INPUTP | 6 | 6 | 159 | 19 | 21 | 18 | 29
EQ | 14 | 
   led<5>.T = !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_5_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(p0<1>.PIN) & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(led_5_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & inter_add<1> & 
	p0<2>.PIN & !(inter_add<2>) & inter_add<3> & 
	!(led_5_obuf.FBK.LFBK)
	# !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	p0<1>.PIN & inter_add<1> & !(p0<2>.PIN) & !(inter_add<2>) & 
	inter_add<3> & led_5_obuf.FBK.LFBK;
   led<5>.CLK = !(wr);
   led<5>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 5 | 8 | load_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 5 | 8
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | load_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 5 | 8
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 6 | 
   load.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) & 
	inter_add<1> & !(inter_add<2>) & !(inter_add<3>) & !(load_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	inter_add<1> & !(inter_add<2>) & !(inter_add<3>) & load_obuf.FBK.LFBK;
   load.CLK = !(wr);
   load.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 4 | 5 | m_s_out_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 4 | 5
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | m_s_out_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 4 | 5
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   m_s_out.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	inter_add<1> & inter_add<2> & !(inter_add<3>) & 
	!(m_s_out_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	inter_add<1> & inter_add<2> & !(inter_add<3>) & 
	m_s_out_obuf.FBK.LFBK;
   m_s_out.CLK = !(wr);
   m_s_out.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 4 | outputh_8_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 4
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | outputh_8_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 4
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   outputh<8>.T = !(cs) & !(reset) & p0<0>.PIN & !(inter_add<0>) & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(outputh_8_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & !(inter_add<0>) & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	outputh_8_obuf.FBK.LFBK;
   outputh<8>.CLK = !(wr);
   outputh<8>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 1 | outputh_9_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 1
INPUTS | 9 | cs  | reset  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | outputh_9_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 1
INPUTP | 4 | 6 | 159 | 19 | 29
EQ | 8 | 
   outputh<9>.T = !(cs) & !(reset) & !(inter_add<0>) & p0<1>.PIN & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	!(outputh_9_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(inter_add<0>) & !(p0<1>.PIN) & 
	inter_add<1> & !(inter_add<2>) & inter_add<3> & 
	outputh_9_obuf.FBK.LFBK;
   outputh<9>.CLK = !(wr);
   outputh<9>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 16 | outputl_0_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 16
INPUTS | 9 | cs  | reset  | p0<0>.PIN  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | outputl_0_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 16
INPUTP | 4 | 6 | 159 | 18 | 29
EQ | 8 | 
   outputl<0>.T = !(cs) & !(reset) & p0<0>.PIN & inter_add<0> & 
	!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & 
	!(outputl_0_obuf.FBK.LFBK)
	# !(cs) & !(reset) & !(p0<0>.PIN) & inter_add<0> & 
	!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & 
	outputl_0_obuf.FBK.LFBK;
   outputl<0>.CLK = !(wr);
   outputl<0>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 14 | outputl_1_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 14
INPUTS | 9 | cs  | reset  | inter_add<0>  | p0<1>.PIN  | inter_add<1>  | inter_add<2>  | inter_add<3>  | wr  | outputl_1_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 14
INPUTP | 4 | 6 | 159 | 19 | 29
EQ | 8 | 
   outputl<1>.T = !(cs) & !(reset) & inter_add<0> & p0<1>.PIN & 
	!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & 
	!(outputl_1_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(p0<1>.PIN) & 
	!(inter_add<1>) & !(inter_add<2>) & inter_add<3> & 
	outputl_1_obuf.FBK.LFBK;
   outputl<1>.CLK = !(wr);
   outputl<1>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 13 | outputl_2_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 13
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | p0<2>.PIN  | inter_add<2>  | inter_add<3>  | wr  | outputl_2_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 13
INPUTP | 4 | 6 | 159 | 21 | 29
EQ | 8 | 
   outputl<2>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	p0<2>.PIN & !(inter_add<2>) & inter_add<3> & 
	!(outputl_2_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(p0<2>.PIN) & !(inter_add<2>) & inter_add<3> & 
	outputl_2_obuf.FBK.LFBK;
   outputl<2>.CLK = !(wr);
   outputl<2>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 11 | outputl_3_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 11
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | p0<3>.PIN  | inter_add<3>  | wr  | outputl_3_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 11
INPUTP | 4 | 6 | 159 | 22 | 29
EQ | 8 | 
   outputl<3>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & p0<3>.PIN & inter_add<3> & 
	!(outputl_3_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & !(p0<3>.PIN) & inter_add<3> & 
	outputl_3_obuf.FBK.LFBK;
   outputl<3>.CLK = !(wr);
   outputl<3>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 10 | outputl_4_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 10
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<4>.PIN  | wr  | outputl_4_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 10
INPUTP | 4 | 6 | 159 | 23 | 29
EQ | 8 | 
   outputl<4>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<4>.PIN & 
	!(outputl_4_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<4>.PIN) & 
	outputl_4_obuf.FBK.LFBK;
   outputl<4>.CLK = !(wr);
   outputl<4>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 8 | outputl_5_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 8
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<5>.PIN  | wr  | outputl_5_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 8
INPUTP | 4 | 6 | 159 | 24 | 29
EQ | 8 | 
   outputl<5>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<5>.PIN & 
	!(outputl_5_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<5>.PIN) & 
	outputl_5_obuf.FBK.LFBK;
   outputl<5>.CLK = !(wr);
   outputl<5>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 7 | outputl_6_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 7
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<6>  | wr  | outputl_6_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 7
INPUTP | 4 | 6 | 159 | 26 | 29
EQ | 6 | 
   outputl<6>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<6> & !(outputl_6_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<6>) & outputl_6_obuf.FBK.LFBK;
   outputl<6>.CLK = !(wr);
   outputl<6>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset

MACROCELL | 7 | 5 | outputl_7_obuf
ATTRIBUTES | 4657954 | 0
OUTPUTMC | 1 | 7 | 5
INPUTS | 9 | cs  | reset  | inter_add<0>  | inter_add<1>  | inter_add<2>  | inter_add<3>  | p0<7>  | wr  | outputl_7_obuf.FBK.LFBK
INPUTMC | 5 | 5 | 17 | 5 | 15 | 5 | 12 | 5 | 9 | 7 | 5
INPUTP | 4 | 6 | 159 | 28 | 29
EQ | 6 | 
   outputl<7>.T = !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & p0<7> & !(outputl_7_obuf.FBK.LFBK)
	# !(cs) & !(reset) & inter_add<0> & !(inter_add<1>) & 
	!(inter_add<2>) & inter_add<3> & !(p0<7>) & outputl_7_obuf.FBK.LFBK;
   outputl<7>.CLK = !(wr);
   outputl<7>.AP = reset;	// GSR
GLOBALS | 1 | 1 | reset