d4_16.mod

此文件是对xilinx95144器件编的程序

MODEL
MODEL_VERSION "v1998.8";
DESIGN "d4_16";

/* port names and type */
INPUT S:PIN99 = cs;
INPUT S:PIN66 = reset;
INPUT S:PIN34 = din<3>;
INPUT S:PIN97 = din<2>;
INPUT S:PIN31 = din<1>;
INPUT S:PIN70 = din<0>;
OUTPUT S:PIN26 = cs_out<0>;
OUTPUT S:PIN37 = cs_out<11>;
OUTPUT S:PIN76 = cs_out<12>;
OUTPUT S:PIN95 = cs_out<15>;
OUTPUT S:PIN16 = cs_out<3>;
OUTPUT S:PIN19 = cs_out<4>;
OUTPUT S:PIN58 = cs_out<7>;
OUTPUT S:PIN8 = cs_out<8>;
OUTPUT S:PIN89 = cs_out<10>;
OUTPUT S:PIN52 = cs_out<13>;
OUTPUT S:PIN65 = cs_out<14>;
OUTPUT S:PIN82 = cs_out<1>;
OUTPUT S:PIN13 = cs_out<2>;
OUTPUT S:PIN32 = cs_out<5>;
OUTPUT S:PIN43 = cs_out<6>;
OUTPUT S:PIN11 = cs_out<9>;

/* timing arc definitions */
cs_cs_out<0>_delay: DELAY cs cs_out<0>;
reset_cs_out<0>_delay: DELAY reset cs_out<0>;
din<3>_cs_out<0>_delay: DELAY din<3> cs_out<0>;
din<2>_cs_out<0>_delay: DELAY din<2> cs_out<0>;
din<1>_cs_out<0>_delay: DELAY din<1> cs_out<0>;
din<0>_cs_out<0>_delay: DELAY din<0> cs_out<0>;
cs_cs_out<10>_delay: DELAY cs cs_out<10>;
din<2>_cs_out<10>_delay: DELAY din<2> cs_out<10>;
din<0>_cs_out<10>_delay: DELAY din<0> cs_out<10>;
reset_cs_out<10>_delay: DELAY reset cs_out<10>;
din<3>_cs_out<10>_delay: DELAY din<3> cs_out<10>;
din<1>_cs_out<10>_delay: DELAY din<1> cs_out<10>;
din<0>_cs_out<11>_delay: DELAY din<0> cs_out<11>;
din<1>_cs_out<11>_delay: DELAY din<1> cs_out<11>;
din<3>_cs_out<11>_delay: DELAY din<3> cs_out<11>;
din<2>_cs_out<11>_delay: DELAY din<2> cs_out<11>;
reset_cs_out<11>_delay: DELAY reset cs_out<11>;
cs_cs_out<11>_delay: DELAY cs cs_out<11>;
cs_cs_out<12>_delay: DELAY cs cs_out<12>;
reset_cs_out<12>_delay: DELAY reset cs_out<12>;
din<3>_cs_out<12>_delay: DELAY din<3> cs_out<12>;
din<2>_cs_out<12>_delay: DELAY din<2> cs_out<12>;
din<1>_cs_out<12>_delay: DELAY din<1> cs_out<12>;
din<0>_cs_out<12>_delay: DELAY din<0> cs_out<12>;
din<3>_cs_out<13>_delay: DELAY din<3> cs_out<13>;
reset_cs_out<13>_delay: DELAY reset cs_out<13>;
din<1>_cs_out<13>_delay: DELAY din<1> cs_out<13>;
din<2>_cs_out<13>_delay: DELAY din<2> cs_out<13>;
din<0>_cs_out<13>_delay: DELAY din<0> cs_out<13>;
cs_cs_out<13>_delay: DELAY cs cs_out<13>;
din<0>_cs_out<14>_delay: DELAY din<0> cs_out<14>;
cs_cs_out<14>_delay: DELAY cs cs_out<14>;
din<3>_cs_out<14>_delay: DELAY din<3> cs_out<14>;
reset_cs_out<14>_delay: DELAY reset cs_out<14>;
din<2>_cs_out<14>_delay: DELAY din<2> cs_out<14>;
din<1>_cs_out<14>_delay: DELAY din<1> cs_out<14>;
din<3>_cs_out<15>_delay: DELAY din<3> cs_out<15>;
cs_cs_out<15>_delay: DELAY cs cs_out<15>;
reset_cs_out<15>_delay: DELAY reset cs_out<15>;
din<0>_cs_out<15>_delay: DELAY din<0> cs_out<15>;
din<1>_cs_out<15>_delay: DELAY din<1> cs_out<15>;
din<2>_cs_out<15>_delay: DELAY din<2> cs_out<15>;
cs_cs_out<1>_delay: DELAY cs cs_out<1>;
reset_cs_out<1>_delay: DELAY reset cs_out<1>;
din<0>_cs_out<1>_delay: DELAY din<0> cs_out<1>;
din<3>_cs_out<1>_delay: DELAY din<3> cs_out<1>;
din<2>_cs_out<1>_delay: DELAY din<2> cs_out<1>;
din<1>_cs_out<1>_delay: DELAY din<1> cs_out<1>;
din<0>_cs_out<2>_delay: DELAY din<0> cs_out<2>;
din<3>_cs_out<2>_delay: DELAY din<3> cs_out<2>;
reset_cs_out<2>_delay: DELAY reset cs_out<2>;
cs_cs_out<2>_delay: DELAY cs cs_out<2>;
din<1>_cs_out<2>_delay: DELAY din<1> cs_out<2>;
din<2>_cs_out<2>_delay: DELAY din<2> cs_out<2>;
din<0>_cs_out<3>_delay: DELAY din<0> cs_out<3>;
din<1>_cs_out<3>_delay: DELAY din<1> cs_out<3>;
cs_cs_out<3>_delay: DELAY cs cs_out<3>;
din<2>_cs_out<3>_delay: DELAY din<2> cs_out<3>;
din<3>_cs_out<3>_delay: DELAY din<3> cs_out<3>;
reset_cs_out<3>_delay: DELAY reset cs_out<3>;
din<2>_cs_out<4>_delay: DELAY din<2> cs_out<4>;
cs_cs_out<4>_delay: DELAY cs cs_out<4>;
reset_cs_out<4>_delay: DELAY reset cs_out<4>;
din<3>_cs_out<4>_delay: DELAY din<3> cs_out<4>;
din<1>_cs_out<4>_delay: DELAY din<1> cs_out<4>;
din<0>_cs_out<4>_delay: DELAY din<0> cs_out<4>;
cs_cs_out<5>_delay: DELAY cs cs_out<5>;
din<0>_cs_out<5>_delay: DELAY din<0> cs_out<5>;
din<1>_cs_out<5>_delay: DELAY din<1> cs_out<5>;
din<2>_cs_out<5>_delay: DELAY din<2> cs_out<5>;
din<3>_cs_out<5>_delay: DELAY din<3> cs_out<5>;
reset_cs_out<5>_delay: DELAY reset cs_out<5>;
din<0>_cs_out<6>_delay: DELAY din<0> cs_out<6>;
din<1>_cs_out<6>_delay: DELAY din<1> cs_out<6>;
din<2>_cs_out<6>_delay: DELAY din<2> cs_out<6>;
din<3>_cs_out<6>_delay: DELAY din<3> cs_out<6>;
reset_cs_out<6>_delay: DELAY reset cs_out<6>;
cs_cs_out<6>_delay: DELAY cs cs_out<6>;
din<0>_cs_out<7>_delay: DELAY din<0> cs_out<7>;
cs_cs_out<7>_delay: DELAY cs cs_out<7>;
reset_cs_out<7>_delay: DELAY reset cs_out<7>;
din<3>_cs_out<7>_delay: DELAY din<3> cs_out<7>;
din<2>_cs_out<7>_delay: DELAY din<2> cs_out<7>;
din<1>_cs_out<7>_delay: DELAY din<1> cs_out<7>;
din<1>_cs_out<8>_delay: DELAY din<1> cs_out<8>;
din<2>_cs_out<8>_delay: DELAY din<2> cs_out<8>;
din<3>_cs_out<8>_delay: DELAY din<3> cs_out<8>;
reset_cs_out<8>_delay: DELAY reset cs_out<8>;
cs_cs_out<8>_delay: DELAY cs cs_out<8>;
din<0>_cs_out<8>_delay: DELAY din<0> cs_out<8>;
cs_cs_out<9>_delay: DELAY cs cs_out<9>;
reset_cs_out<9>_delay: DELAY reset cs_out<9>;
din<3>_cs_out<9>_delay: DELAY din<3> cs_out<9>;
din<2>_cs_out<9>_delay: DELAY din<2> cs_out<9>;
din<1>_cs_out<9>_delay: DELAY din<1> cs_out<9>;
din<0>_cs_out<9>_delay: DELAY din<0> cs_out<9>;

/* timing check arc definitions */

ENDMODEL