📄 tba_2472.rpt
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cpldfit: version F.31 Xilinx Inc.
Fitter Report
Design Name: tba_2472 Date: 8-11-2004, 11:48AM
Device Used: XC95144-7-PQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
46 /144 ( 32%) 119 /720 ( 17%) 30 /144 ( 21%) 53 /81 ( 65%) 95 /288 ( 33%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 16 16 | I/O : 50 23
Output : 30 30 | GCK/IO : 0 3
Bidirectional : 6 6 | GTS/IO : 2 2
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 53 53
MACROCELL RESOURCES:
Total Macrocells Available 144
Registered Macrocells 30
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Signal 'reset' mapped onto global set/reset net GSR.
POWER DATA:
There are 46 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 46 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
$OpTx$FX_DC$11 2 3 FB8_18 STD (b) (b)
check<0> 2 9 FB7_15 STD FAST 62 I/O O RESET
check<1> 2 9 FB7_11 STD FAST 58 I/O O RESET
check<2> 2 9 FB7_9 STD FAST 57 I/O O RESET
en485 3 9 FB4_9 STD FAST 94 I/O O RESET
inter_add<0> 3 3 FB6_18 STD (b) (b) RESET
inter_add<1> 3 3 FB6_16 STD (b) (b) RESET
inter_add<2> 3 3 FB6_13 STD (b) (b) RESET
inter_add<3> 3 3 FB6_10 STD (b) (b) RESET
lcd_c 3 9 FB7_8 STD FAST 56 I/O O RESET
led1 3 9 FB6_17 STD FAST 88 I/O O RESET
led<2> 5 11 FB6_15 STD FAST 87 I/O O RESET
led<3> 5 11 FB6_14 STD FAST 84 I/O O RESET
led<4> 5 11 FB6_12 STD FAST 83 I/O O RESET
led<5> 5 11 FB6_11 STD FAST 82 I/O O RESET
ledd<0> 0 0 FB4_2 STD FAST 89 I/O O
ledd<1> 0 0 FB4_5 STD FAST 91 I/O O
ledd<2> 0 0 FB4_6 STD FAST 92 I/O O
ledd<3> 0 0 FB4_8 STD FAST 93 I/O O
load 3 9 FB6_9 STD FAST 81 I/O O RESET
m_s_out 3 9 FB5_6 STD FAST 39 I/O O RESET
outputh<8> 3 9 FB8_5 STD FAST 66 I/O O RESET
outputh<9> 3 9 FB8_2 STD FAST 65 I/O O RESET
outputl<0> 3 9 FB8_17 STD FAST 75 I/O O RESET
outputl<1> 3 9 FB8_15 STD FAST 74 I/O O RESET
outputl<2> 3 9 FB8_14 STD FAST 73 I/O O RESET
outputl<3> 3 9 FB8_12 STD FAST 72 I/O O RESET
outputl<4> 3 9 FB8_11 STD FAST 70 I/O O RESET
outputl<5> 3 9 FB8_9 STD FAST 69 I/O O RESET
outputl<6> 3 9 FB8_8 STD FAST 68 I/O O RESET
outputl<7> 3 9 FB8_6 STD FAST 67 I/O O RESET
p0<0> 2 11 FB1_2 STD FAST 13 I/O I/O
p0<1> 2 8 FB1_3 STD FAST 14 I/O I/O
p0<2> 2 8 FB1_5 STD FAST 15 I/O I/O
p0<3> 2 8 FB1_6 STD FAST 16 I/O I/O
p0<4> 2 8 FB1_8 STD FAST 17 I/O I/O
p0<5> 2 8 FB1_9 STD FAST 18 I/O I/O
p0_0_iobufe$WA0 2 8 FB8_16 STD (b) (b)
p0_0_iobufe$WA1 2 8 FB8_13 STD (b) (b)
p0_0_iobufe$WA2 2 8 FB8_10 STD (b) (b)
p0_0_iobufe$WA3 2 8 FB8_7 STD (b) (b)
p0_0_iobufe$WA4 2 8 FB8_4 STD (b) (b)
pa_c 3 9 FB5_5 STD FAST 38 I/O O RESET
play_s 3 9 FB7_5 STD FAST 54 I/O O RESET
stop_s 3 9 FB7_2 STD FAST 52 I/O O RESET
updown 3 9 FB7_17 STD FAST 63 I/O O RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
ale FB2_5 3 GTS/I/O I
cs FB2_8 5 GTS/I/O I
m_s_in FB5_8 41 I/O I
nofile FB7_12 60 I/O I
p0<6> FB1_11 19 I/O I
p0<7> FB1_12 20 I/O I
playing FB7_14 61 I/O I
radio FB7_6 55 I/O I
rd FB1_15 22 I/O I
reset FB2_2 1 GSR/I/O GSR/I
speed<0> FB5_17 51 I/O I
speed<1> FB5_15 48 I/O I
speed<2> FB5_14 45 I/O I
speed<3> FB5_12 44 I/O I
speed<4> FB5_11 43 I/O I
speed<5> FB5_9 42 I/O I
wr FB1_14 21 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 6 14 19 12 0/6 11
FB2 0 0 0 0 0/0 10
FB3 0 0 0 0 0/0 10
FB4 5 9 9 3 5/0 10
FB5 2 10 10 6 2/0 10
FB6 10 18 18 38 6/0 10
FB7 7 13 13 18 7/0 10
FB8 16 31 31 42 10/0 10
---- ----- ----- -----
46 119 30/6 81
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 14/22
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
p0<0> 2 0 0 3 FB1_2 STD 13 I/O I/O
p0<1> 2 0 0 3 FB1_3 STD 14 I/O I/O
(unused) 0 0 0 5 FB1_4 (b)
p0<2> 2 0 0 3 FB1_5 STD 15 I/O I/O
p0<3> 2 0 0 3 FB1_6 STD 16 I/O I/O
(unused) 0 0 0 5 FB1_7 (b)
p0<4> 2 0 0 3 FB1_8 STD 17 I/O I/O
p0<5> 2 0 0 3 FB1_9 STD 18 I/O I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 19 I/O I
(unused) 0 0 0 5 FB1_12 20 I/O I
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 21 I/O I
(unused) 0 0 0 5 FB1_15 22 I/O I
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 24 GCK/I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$11 8: p0_0_iobufe$WA0 14: reset
2: cs 9: p0_0_iobufe$WA1 15: speed<1>
3: inter_add<0> 10: p0_0_iobufe$WA2 16: speed<2>
4: inter_add<1> 11: p0_0_iobufe$WA3 17: speed<3>
5: inter_add<2> 12: p0_0_iobufe$WA4 18: speed<4>
6: inter_add<3> 13: rd 19: speed<5>
7: p0_0_iobufe
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
p0<0> XX...XX@@@@@XX.......................... 11 6
p0<1> .XXXXX......XXX......................... 8 8
p0<2> .XXXXX......XX.X........................ 8 8
p0<3> .XXXXX......XX..X....................... 8 8
p0<4> .XXXXX......XX...X...................... 8 8
p0<5> .XXXXX......XX....X..................... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 1 GSR/I/O GSR/I
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 3 GTS/I/O I
(unused) 0 0 0 5 FB2_6 4 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O I
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 8 I/O
(unused) 0 0 0 5 FB2_12 9 I/O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 10 I/O
(unused) 0 0 0 5 FB2_15 11 I/O
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 12 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 25 GCK/I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 26 I/O
(unused) 0 0 0 5 FB3_6 27 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 29 GCK/I/O
(unused) 0 0 0 5 FB3_9 30 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 31 I/O
(unused) 0 0 0 5 FB3_12 32 I/O
(unused) 0 0 0 5 FB3_13 (b)
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