tba_2470.syr

此文件是对xilinx95144器件编的程序

Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: tba_2470.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : tba_2470.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : tba_2470
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Entity Name                        : tba_2470
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower

---- Other Options
cross_clock_analysis               : NO
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/tba2472BCPLD源程序/d4_16.vhd in Library work.
Architecture behavioral of Entity d4_16 is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/reg.vhd in Library work.
Architecture behavioral of Entity reg is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/latch.vhd in Library work.
Architecture behavioral of Entity latch is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/reg2_4.vhd in Library work.
Architecture behavioral of Entity reg2_4 is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/reg_2_3.vhd in Library work.
Architecture behavioral of Entity reg2_3 is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/regd.vhd in Library work.
Architecture behavioral of Entity regd is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/regdd.vhd in Library work.
Architecture behavioral of Entity regdd is up to date.
Compiling vhdl file G:/tba2472BCPLD源程序/tba-2470.vhd in Library work.
Architecture behavioral of Entity tba_2470 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <tba_2470> (Architecture <behavioral>).
Entity <tba_2470> analyzed. Unit <tba_2470> generated.

Analyzing Entity <d4_16> (Architecture <behavioral>).
INFO:Xst:1561 - G:/tba2472BCPLD源程序/d4_16.vhd line 41: Mux is complete : default of case is discarded
Entity <d4_16> analyzed. Unit <d4_16> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 1
Entity <reg> analyzed. Unit <reg> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 8
Entity <reg> analyzed. Unit <reg0> generated.

Analyzing generic Entity <latch> (Architecture <behavioral>).
	size = 4
Entity <latch> analyzed. Unit <latch> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 2
Entity <reg> analyzed. Unit <reg1> generated.

Analyzing Entity <reg2_4> (Architecture <behavioral>).
INFO:Xst:1561 - G:/tba2472BCPLD源程序/reg2_4.vhd line 29: Mux is complete : default of case is discarded
Entity <reg2_4> analyzed. Unit <reg2_4> generated.

Analyzing Entity <reg2_3> (Architecture <behavioral>).
Entity <reg2_3> analyzed. Unit <reg2_3> generated.

Analyzing generic Entity <regd> (Architecture <behavioral>).
	size = 7
Entity <regd> analyzed. Unit <regd> generated.

Analyzing Entity <regdd> (Architecture <behavioral>).
Entity <regdd> analyzed. Unit <regdd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <regdd>.
    Related source file is G:/tba2472BCPLD源程序/regdd.vhd.
    Found 1-bit tristate buffer for signal <dout>.
    Summary:
	inferred   1 Tristate(s).
Unit <regdd> synthesized.


Synthesizing Unit <regd>.
    Related source file is G:/tba2472BCPLD源程序/regd.vhd.
    Found 7-bit tristate buffer for signal <dout>.
    Summary:
	inferred   7 Tristate(s).
Unit <regd> synthesized.


Synthesizing Unit <reg2_3>.
    Related source file is G:/tba2472BCPLD源程序/reg_2_3.vhd.
    Found 3-bit register for signal <dout>.
Unit <reg2_3> synthesized.


Synthesizing Unit <reg2_4>.
    Related source file is G:/tba2472BCPLD源程序/reg2_4.vhd.
    Found 4-bit register for signal <dout>.
Unit <reg2_4> synthesized.


Synthesizing Unit <reg1>.
    Related source file is G:/tba2472BCPLD源程序/reg.vhd.
    Found 2-bit register for signal <dout>.
Unit <reg1> synthesized.


Synthesizing Unit <latch>.
    Related source file is G:/tba2472BCPLD源程序/latch.vhd.
    Found 4-bit tristate buffer for signal <dout>.
    Found 4-bit register for signal <Mtridata_dout> created at line 18.
    Summary:
	inferred   4 Tristate(s).
Unit <latch> synthesized.


Synthesizing Unit <reg0>.
    Related source file is G:/tba2472BCPLD源程序/reg.vhd.
    Found 8-bit register for signal <dout>.
Unit <reg0> synthesized.


Synthesizing Unit <reg>.
    Related source file is G:/tba2472BCPLD源程序/reg.vhd.
    Found 1-bit register for signal <dout<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <reg> synthesized.


Synthesizing Unit <d4_16>.
    Related source file is G:/tba2472BCPLD源程序/d4_16.vhd.
Unit <d4_16> synthesized.


Synthesizing Unit <tba_2470>.
    Related source file is G:/tba2472BCPLD源程序/tba-2470.vhd.
WARNING:Xst:652 - Inout <p0<7>> is used but never assigned.
WARNING:Xst:646 - Signal <cs_reg<15>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_reg<14>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_reg<13>> is assigned but never used.
Unit <tba_2470> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 14
  3-bit register                   : 1
  1-bit register                   : 9
  4-bit register                   : 2
  2-bit register                   : 1
  8-bit register                   : 1
# Tristates                        : 7
  1-bit tristate buffer            : 5
  4-bit tristate buffer            : 1
  7-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted
WARNING:Xst:1348 - Unit regd is merged (output interface has tristates)
WARNING:Xst:1348 - Unit regdd is merged (output interface has tristates)

Optimizing unit <tba_2470> ...

Optimizing unit <d4_16> ...

Optimizing unit <reg> ...

Optimizing unit <reg0> ...

Optimizing unit <latch> ...
  implementation constraint: iob	 : Mtridata_dout<1>
  implementation constraint: KEEP	 : Mtridata_dout<1>
  implementation constraint: iob	 : Mtridata_dout<0>
  implementation constraint: KEEP	 : Mtridata_dout<0>
  implementation constraint: iob	 : Mtridata_dout<3>
  implementation constraint: KEEP	 : Mtridata_dout<3>
  implementation constraint: iob	 : Mtridata_dout<2>
  implementation constraint: KEEP	 : Mtridata_dout<2>

Optimizing unit <reg1> ...

Optimizing unit <reg2_4> ...

Optimizing unit <reg2_3> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : tba_2470.ngr
Top Level Output File Name         : tba_2470
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : YES
Macro Generator                    : macro+
Target Technology                  : xc9500
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 54

Macro Statistics :
# Registers                        : 24
#      1-bit register              : 24
# Tristates                        : 7
#      1-bit tristate buffer       : 5
#      4-bit tristate buffer       : 1
#      7-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 222
#      AND2                        : 66
#      AND6                        : 1
#      INV                         : 86
#      OR2                         : 58
#      OR3                         : 9
#      OR4                         : 1
#      VCC                         : 1
# FlipFlops/Latches                : 30
#      FD                          : 4
#      FDP                         : 26
# Tri-States                       : 10
#      BUFE                        : 10
# IO Buffers                       : 54
#      IBUF                        : 18
#      IOBUFE                      : 7
#      OBUF                        : 29
=========================================================================
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Total memory usage is 49880 kilobytes