mcs51.h

circuit calculation program

/* Table of opcodes for the Motorola M88k family.
   Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc.

This file is part of GDB and GAS.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

/*
 *			Disassembler Instruction Table
 *
 *	The first field of the table is the opcode field. If an opcode
 *	is specified which has any non-opcode bits on, a system error
 *	will occur when the system attempts the install it into the
 *	instruction table.  The second parameter is a pointer to the
 *	instruction mnemonic. Each operand is specified by offset, width,
 *	and type. The offset is the bit number of the least significant
 *	bit of the operand with bit 0 being the least significant bit of
 *	the instruction. The width is the number of bits used to specify
 *	the operand. The type specifies the output format to be used for
 *	the operand. The valid formats are: register, register indirect,
 *	hex constant, and bit field specification.  The last field is a
 *	pointer to the next instruction in the linked list.  These pointers
 *	are initialized by init_disasm().
 *
 *				Revision History
 *
 *	Revision 1.0	11/08/85	Creation date
 *		 1.1	02/05/86	Updated instruction mnemonic table MD
 *		 1.2	06/16/86	Updated SIM_FLAGS for floating point
 *		 1.3	09/20/86	Updated for new encoding
 *		 	05/11/89	R. Trawick adapted from Motorola disassembler
 */

#include <stdio.h>
typedef struct
{
  /* instruction name sans width suffix ("mov" for movl insns) */
  char *name;


  /* how many operands */
  unsigned char op_num;
  unsigned char insn_size;  
  unsigned char op_code;
  unsigned char op_mask;

  /* how many clocks */
  unsigned char clk_num;
  unsigned char mem_type;
  
  /* operand_types[i] describes the type of operand i.  This is made
     by OR'ing together all of the possible type masks.  (e.g.
     'operand_types[i] = Reg|Imm' specifies that operand i can be
     either a register or an immediate operand.  */
  unsigned int op_types[3];
}
template;



/* these are for register name --> number & type hash lookup */
typedef struct
{
  char *reg_name;
  int  reg_type;  /* bit or byte */
  unsigned int reg_num;
  char *reg_desc;  
}
reg_entry;

#define ENCODE_REG(reg) (((reg)->reg_num & 0xffff) | ((reg)->reg_type << 16))
#define ENCODE_REG0(a,b) (((b) & 0xffff) | (a) << 16)
#define DECODE_REG(a,reg) {(reg)->reg_num = (a) & 0xffff; reg->reg_type = (a) >> 16;}

#define REG_TYPE(a) ((a)>>16)
#define REG_NUM(a) ((a)&0xffff)

/*
  'templates' is for grouping together 'template' structures for opcodes
  of the same name.  This is only used for storing the insns in the grand
  ole hash table of insns.
  The templates themselves start at START and range up to (but not including)
  END.
  */
typedef struct
{
  const template *start;
  const template *end;
}
templates;
enum mcs51_operand_type {
	mcs51_none,
	mcs51_A,	
	mcs51_C,		
	mcs51_AB,
	mcs51_bit,
	mcs51_not_bit,	
	mcs51_mem8,
	mcs51_mem16,	
	mcs51_mem16_x,	
	mcs51_mem16_p,		
	mcs51_Rn,
	mcs51_dptr,	
	mcs51_direct,
	mcs51_imm8,	
	mcs51_imm16,	
	mcs51_addr8,				
	mcs51_addr11,					
	mcs51_addr16						
};	

enum mcs51_operand_encode {
	mcs51_notcoded   = 0,
	mcs51_implied    = 0,
	mcs51_oct_1      = 1<<16,	      /* hard code 1 byte to oct 1*/
	mcs51_oct_2      = 2<<16,	      /* hard code 1 byte to oct 2*/	
	mcs51_2oct_1     = 3<<16,	      /* hard code 1 word to oct 1*/
		
	mcs51_or1_0      = 4<<16,              /* or to the lowest 1 bit  of oct 0 */ 
	mcs51_or3_0      = 5<<16,              /* or to the lowest 3 bits of oct 0 */
	mcs51_pcrel8_1   = 6<<16,	       /* gen pcrel reloc @ oct 1*/  
	mcs51_pcrel8_2   = 7<<16,              /* gen pcrel reloc @ oct 2*/
	mcs51_reloc11    = 8<<16,	       /* gen pcrel reloc @ oct 0*/
	mcs51_reloc16    = 9<<16,              /* gen reloc if symbol, hard code imm if not-symbol constant*/
	mcs51_reloc16b   =10<<16
};	

#define OPERAND_TYPE(a) ((a)&0xffff)
#define OPERAND_ENCODE(a) ((a)&0xff0000)


static template mcs51_optab[] = {
	{ "nop",  0, 1, 0,   0xff, 1,{mcs51_notcoded| 0,            mcs51_notcoded| 0,            mcs51_notcoded| 0}},															
		
	{ "mov",  2, 1, 0xe8,0xf8, 1,{mcs51_implied | mcs51_A,      mcs51_or3_0   | mcs51_Rn,     mcs51_notcoded| 0}},
	{ NULL,   2, 2, 0xe5,0xff, 1,{mcs51_implied | mcs51_A,      mcs51_oct_1   | mcs51_direct, mcs51_notcoded| 0}},	
	{ NULL,   2, 1, 0xe6,0xfe, 1,{mcs51_implied | mcs51_A,      mcs51_or1_0   | mcs51_mem8,   mcs51_notcoded| 0}},		

			
	{ NULL,   2, 2, 0x74,0xff, 1,{mcs51_implied | mcs51_A,      mcs51_oct_1   | mcs51_imm8,   mcs51_notcoded| 0}},				
	{ NULL,   2, 2, 0x78,0xf8, 1,{mcs51_or3_0   | mcs51_Rn,     mcs51_oct_1   | mcs51_imm8,   mcs51_notcoded| 0}},					
	{ NULL,   2, 3, 0x75,0xff, 2,{mcs51_oct_1   | mcs51_direct, mcs51_oct_2   | mcs51_imm8,   mcs51_notcoded| 0}},								
	{ NULL,   2, 2, 0x76,0xfe, 1,{mcs51_or1_0   | mcs51_mem8,   mcs51_oct_1   | mcs51_imm8,   mcs51_notcoded| 0}},								


	{ NULL,   2, 1, 0xf8,0xf8, 1,{mcs51_or3_0   | mcs51_Rn,     mcs51_implied | mcs51_A,      mcs51_notcoded| 0}},				
	{ NULL,   2, 2, 0xf5,0xff, 1,{mcs51_oct_1   | mcs51_direct, mcs51_implied | mcs51_A,      mcs51_notcoded| 0}},					
	{ NULL,   2, 1, 0xf6,0xfe, 1,{mcs51_or1_0   | mcs51_mem8,   mcs51_implied | mcs51_A,      mcs51_notcoded| 0}},								

	{ NULL,   2, 2, 0x88,0xf8, 2,{mcs51_oct_1   | mcs51_direct, mcs51_or3_0   | mcs51_Rn,     mcs51_notcoded| 0}},							
	{ NULL,   2, 3, 0x85,0xff, 2,{mcs51_oct_1   | mcs51_direct, mcs51_oct_2   | mcs51_direct, mcs51_notcoded| 0}},						
	{ NULL,   2, 2, 0x86,0xfe, 2,{mcs51_oct_1   | mcs51_direct, mcs51_or1_0   | mcs51_mem8,   mcs51_notcoded| 0}},						


	
	{ NULL,   2, 2, 0xa2,0xff, 1,{mcs51_implied | mcs51_C,      mcs51_oct_1   | mcs51_bit,    mcs51_notcoded| 0}},										
	{ NULL,   2, 3, 0xa6,0xfe, 2,{mcs51_or1_0   | mcs51_mem8,   mcs51_oct_1   | mcs51_direct, mcs51_notcoded| 0}},