mcs_51.map.qmsg

VHDL实现：单片机与FPGA接口通信源文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 13 15:32:38 2005 " "Info: Processing started: Sat Aug 13 15:32:38 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off mcs_51 -c mcs_51 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off mcs_51 -c mcs_51" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mcs_51.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mcs_51.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mcs_51-ART " "Info: Found design unit 1: mcs_51-ART" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 mcs_51 " "Info: Found entity 1: mcs_51" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MCS_51_CPLD.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file MCS_51_CPLD.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 MCS_51_CPLD " "Info: Found entity 1: MCS_51_CPLD" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { } } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WR mcs_51.vhd(32) " "Warning: VHDL Process Statement warning at mcs_51.vhd(32): signal \"WR\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WR mcs_51.vhd(47) " "Warning: VHDL Process Statement warning at mcs_51.vhd(47): signal \"WR\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "LATCH_IN1 mcs_51.vhd(63) " "Warning: VHDL Process Statement warning at mcs_51.vhd(63): signal \"LATCH_IN1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 63 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "91 " "Info: Implemented 91 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "21 " "Info: Implemented 21 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "45 " "Info: Implemented 45 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 13 15:32:41 2005 " "Info: Processing ended: Sat Aug 13 15:32:41 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}