📄 mcs_51.tan.qmsg
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{ "Info" "ITAN_NO_REG2REG_EXIST" "P2\[7\] " "Info: No valid register-to-register data paths exist for clock \"P2\[7\]\"" { } { } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "P2\[5\] " "Info: No valid register-to-register data paths exist for clock \"P2\[5\]\"" { } { } 0}
{ "Info" "ITDB_TSU_RESULT" "mcs_51:inst\|LATCH_ADDRES\[5\] P0\[5\] ALE 9.400 ns register " "Info: tsu for register \"mcs_51:inst\|LATCH_ADDRES\[5\]\" (data pin = \"P0\[5\]\", clock pin = \"ALE\") is 9.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.200 ns + Longest pin register " "Info: + Longest pin to register delay is 11.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns P0\[5\] 1 PIN PIN_81 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'P0\[5\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "" { P0[5] } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 472 648 112 "P0\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns P0~2 2 COMB IOC_81 3 " "Info: 2: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = IOC_81; Fanout = 3; COMB Node = 'P0~2'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "4.900 ns" { P0[5] P0~2 } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 472 648 112 "P0\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(0.800 ns) 11.200 ns mcs_51:inst\|LATCH_ADDRES\[5\] 3 REG LC4_C4 2 " "Info: 3: + IC(5.500 ns) + CELL(0.800 ns) = 11.200 ns; Loc. = LC4_C4; Fanout = 2; REG Node = 'mcs_51:inst\|LATCH_ADDRES\[5\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "6.300 ns" { P0~2 mcs_51:inst|LATCH_ADDRES[5] } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 50.89 % " "Info: Total cell delay = 5.700 ns ( 50.89 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns 49.11 % " "Info: Total interconnect delay = 5.500 ns ( 49.11 % )" { } { } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "11.200 ns" { P0[5] P0~2 mcs_51:inst|LATCH_ADDRES[5] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "11.200 ns" { P0[5] P0~2 mcs_51:inst|LATCH_ADDRES[5] } { 0.000ns 0.000ns 5.500ns } { 0.000ns 4.900ns 0.800ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"ALE\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ALE 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'ALE'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "" { ALE } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 144 -32 136 160 "ALE" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns mcs_51:inst\|LATCH_ADDRES\[5\] 2 REG LC4_C4 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_C4; Fanout = 2; REG Node = 'mcs_51:inst\|LATCH_ADDRES\[5\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "0.400 ns" { ALE mcs_51:inst|LATCH_ADDRES[5] } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "2.400 ns" { ALE mcs_51:inst|LATCH_ADDRES[5] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.400 ns" { ALE ALE~out mcs_51:inst|LATCH_ADDRES[5] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "11.200 ns" { P0[5] P0~2 mcs_51:inst|LATCH_ADDRES[5] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "11.200 ns" { P0[5] P0~2 mcs_51:inst|LATCH_ADDRES[5] } { 0.000ns 0.000ns 5.500ns } { 0.000ns 4.900ns 0.800ns } } } { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "2.400 ns" { ALE mcs_51:inst|LATCH_ADDRES[5] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.400 ns" { ALE ALE~out mcs_51:inst|LATCH_ADDRES[5] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "P2\[1\] DATAOUT1\[3\] mcs_51:inst\|LATCH_OUT1\[3\] 30.000 ns register " "Info: tco from clock \"P2\[1\]\" to destination pin \"DATAOUT1\[3\]\" through register \"mcs_51:inst\|LATCH_OUT1\[3\]\" is 30.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "P2\[1\] source 21.700 ns + Longest register " "Info: + Longest clock path from clock \"P2\[1\]\" to source register is 21.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns P2\[1\] 1 CLK PIN_120 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_120; Fanout = 1; CLK Node = 'P2\[1\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "" { P2[1] } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.400 ns) 8.500 ns mcs_51:inst\|process5~121 2 COMB LC6_C4 1 " "Info: 2: + IC(2.200 ns) + CELL(1.400 ns) = 8.500 ns; Loc. = LC6_C4; Fanout = 1; COMB Node = 'mcs_51:inst\|process5~121'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "3.600 ns" { P2[1] mcs_51:inst|process5~121 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 10.500 ns mcs_51:inst\|process5~122 3 COMB LC2_C4 2 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 10.500 ns; Loc. = LC2_C4; Fanout = 2; COMB Node = 'mcs_51:inst\|process5~122'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "2.000 ns" { mcs_51:inst|process5~121 mcs_51:inst|process5~122 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.600 ns) 14.300 ns mcs_51:inst\|WR_ENABLE1~65 4 COMB LC2_C25 2 " "Info: 4: + IC(2.200 ns) + CELL(1.600 ns) = 14.300 ns; Loc. = LC2_C25; Fanout = 2; COMB Node = 'mcs_51:inst\|WR_ENABLE1~65'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "3.800 ns" { mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.600 ns) 17.200 ns mcs_51:inst\|WR_ENABLE1~0 5 COMB LC1_C26 8 " "Info: 5: + IC(1.300 ns) + CELL(1.600 ns) = 17.200 ns; Loc. = LC1_C26; Fanout = 8; COMB Node = 'mcs_51:inst\|WR_ENABLE1~0'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "2.900 ns" { mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 21.700 ns mcs_51:inst\|LATCH_OUT1\[3\] 6 REG LC8_D15 1 " "Info: 6: + IC(4.500 ns) + CELL(0.000 ns) = 21.700 ns; Loc. = LC8_D15; Fanout = 1; REG Node = 'mcs_51:inst\|LATCH_OUT1\[3\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "4.500 ns" { mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns 51.61 % " "Info: Total cell delay = 11.200 ns ( 51.61 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.500 ns 48.39 % " "Info: Total interconnect delay = 10.500 ns ( 48.39 % )" { } { } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "21.700 ns" { P2[1] mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "21.700 ns" { P2[1] P2[1]~out mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } { 0.000ns 0.000ns 2.200ns 0.300ns 2.200ns 1.300ns 4.500ns } { 0.000ns 4.900ns 1.400ns 1.700ns 1.600ns 1.600ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.800 ns + Longest register pin " "Info: + Longest register to pin delay is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mcs_51:inst\|LATCH_OUT1\[3\] 1 REG LC8_D15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_D15; Fanout = 1; REG Node = 'mcs_51:inst\|LATCH_OUT1\[3\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "" { mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(6.300 ns) 7.800 ns DATAOUT1\[3\] 2 PIN PIN_88 0 " "Info: 2: + IC(1.500 ns) + CELL(6.300 ns) = 7.800 ns; Loc. = PIN_88; Fanout = 0; PIN Node = 'DATAOUT1\[3\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "7.800 ns" { mcs_51:inst|LATCH_OUT1[3] DATAOUT1[3] } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 128 472 649 144 "DATAOUT1\[7..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 80.77 % " "Info: Total cell delay = 6.300 ns ( 80.77 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 19.23 % " "Info: Total interconnect delay = 1.500 ns ( 19.23 % )" { } { } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "7.800 ns" { mcs_51:inst|LATCH_OUT1[3] DATAOUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "7.800 ns" { mcs_51:inst|LATCH_OUT1[3] DATAOUT1[3] } { 0.000ns 1.500ns } { 0.000ns 6.300ns } } } } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "21.700 ns" { P2[1] mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "21.700 ns" { P2[1] P2[1]~out mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } { 0.000ns 0.000ns 2.200ns 0.300ns 2.200ns 1.300ns 4.500ns } { 0.000ns 4.900ns 1.400ns 1.700ns 1.600ns 1.600ns 0.000ns } } } { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "7.800 ns" { mcs_51:inst|LATCH_OUT1[3] DATAOUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "7.800 ns" { mcs_51:inst|LATCH_OUT1[3] DATAOUT1[3] } { 0.000ns 1.500ns } { 0.000ns 6.300ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "P2\[1\] P0\[5\] 23.100 ns Longest " "Info: Longest tpd from source pin \"P2\[1\]\" to destination pin \"P0\[5\]\" is 23.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns P2\[1\] 1 CLK PIN_120 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_120; Fanout = 1; CLK Node = 'P2\[1\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "" { P2[1] } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.400 ns) 8.500 ns mcs_51:inst\|process5~121 2 COMB LC6_C4 1 " "Info: 2: + IC(2.200 ns) + CELL(1.400 ns) = 8.500 ns; Loc. = LC6_C4; Fanout = 1; COMB Node = 'mcs_51:inst\|process5~121'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "3.600 ns" { P2[1] mcs_51:inst|process5~121 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 10.500 ns mcs_51:inst\|process5~122 3 COMB LC2_C4 2 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 10.500 ns; Loc. = LC2_C4; Fanout = 2; COMB Node = 'mcs_51:inst\|process5~122'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "2.000 ns" { mcs_51:inst|process5~121 mcs_51:inst|process5~122 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.600 ns) 14.300 ns mcs_51:inst\|process5~2 4 COMB LC1_C25 8 " "Info: 4: + IC(2.200 ns) + CELL(1.600 ns) = 14.300 ns; Loc. = LC1_C25; Fanout = 8; COMB Node = 'mcs_51:inst\|process5~2'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "3.800 ns" { mcs_51:inst|process5~122 mcs_51:inst|process5~2 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(4.800 ns) 23.100 ns P0\[5\] 5 PIN PIN_81 0 " "Info: 5: + IC(4.000 ns) + CELL(4.800 ns) = 23.100 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'P0\[5\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "8.800 ns" { mcs_51:inst|process5~2 P0[5] } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 472 648 112 "P0\[7..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.400 ns 62.34 % " "Info: Total cell delay = 14.400 ns ( 62.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns 37.66 % " "Info: Total interconnect delay = 8.700 ns ( 37.66 % )" { } { } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "23.100 ns" { P2[1] mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|process5~2 P0[5] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "23.100 ns" { P2[1] P2[1]~out mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|process5~2 P0[5] } { 0.000ns 0.000ns 2.200ns 0.300ns 2.200ns 4.000ns } { 0.000ns 4.900ns 1.400ns 1.700ns 1.600ns 4.800ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "mcs_51:inst\|LATCH_OUT1\[3\] P0\[3\] P2\[1\] 14.900 ns register " "Info: th for register \"mcs_51:inst\|LATCH_OUT1\[3\]\" (data pin = \"P0\[3\]\", clock pin = \"P2\[1\]\") is 14.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "P2\[1\] destination 21.700 ns + Longest register " "Info: + Longest clock path from clock \"P2\[1\]\" to destination register is 21.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns P2\[1\] 1 CLK PIN_120 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_120; Fanout = 1; CLK Node = 'P2\[1\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "" { P2[1] } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.400 ns) 8.500 ns mcs_51:inst\|process5~121 2 COMB LC6_C4 1 " "Info: 2: + IC(2.200 ns) + CELL(1.400 ns) = 8.500 ns; Loc. = LC6_C4; Fanout = 1; COMB Node = 'mcs_51:inst\|process5~121'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "3.600 ns" { P2[1] mcs_51:inst|process5~121 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 10.500 ns mcs_51:inst\|process5~122 3 COMB LC2_C4 2 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 10.500 ns; Loc. = LC2_C4; Fanout = 2; COMB Node = 'mcs_51:inst\|process5~122'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "2.000 ns" { mcs_51:inst|process5~121 mcs_51:inst|process5~122 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.600 ns) 14.300 ns mcs_51:inst\|WR_ENABLE1~65 4 COMB LC2_C25 2 " "Info: 4: + IC(2.200 ns) + CELL(1.600 ns) = 14.300 ns; Loc. = LC2_C25; Fanout = 2; COMB Node = 'mcs_51:inst\|WR_ENABLE1~65'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "3.800 ns" { mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.600 ns) 17.200 ns mcs_51:inst\|WR_ENABLE1~0 5 COMB LC1_C26 8 " "Info: 5: + IC(1.300 ns) + CELL(1.600 ns) = 17.200 ns; Loc. = LC1_C26; Fanout = 8; COMB Node = 'mcs_51:inst\|WR_ENABLE1~0'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "2.900 ns" { mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 21.700 ns mcs_51:inst\|LATCH_OUT1\[3\] 6 REG LC8_D15 1 " "Info: 6: + IC(4.500 ns) + CELL(0.000 ns) = 21.700 ns; Loc. = LC8_D15; Fanout = 1; REG Node = 'mcs_51:inst\|LATCH_OUT1\[3\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "4.500 ns" { mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns 51.61 % " "Info: Total cell delay = 11.200 ns ( 51.61 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.500 ns 48.39 % " "Info: Total interconnect delay = 10.500 ns ( 48.39 % )" { } { } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "21.700 ns" { P2[1] mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "21.700 ns" { P2[1] P2[1]~out mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } { 0.000ns 0.000ns 2.200ns 0.300ns 2.200ns 1.300ns 4.500ns } { 0.000ns 4.900ns 1.400ns 1.700ns 1.600ns 1.600ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns P0\[3\] 1 PIN PIN_19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_19; Fanout = 1; PIN Node = 'P0\[3\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "" { P0[3] } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 472 648 112 "P0\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns P0~4 2 COMB IOC_19 3 " "Info: 2: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = IOC_19; Fanout = 3; COMB Node = 'P0~4'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "4.900 ns" { P0[3] P0~4 } "NODE_NAME" } "" } } { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 472 648 112 "P0\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(0.800 ns) 8.100 ns mcs_51:inst\|LATCH_OUT1\[3\] 3 REG LC8_D15 1 " "Info: 3: + IC(2.400 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_D15; Fanout = 1; REG Node = 'mcs_51:inst\|LATCH_OUT1\[3\]'" { } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "3.200 ns" { P0~4 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 70.37 % " "Info: Total cell delay = 5.700 ns ( 70.37 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 29.63 % " "Info: Total interconnect delay = 2.400 ns ( 29.63 % )" { } { } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "8.100 ns" { P0[3] P0~4 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.100 ns" { P0[3] P0~4 mcs_51:inst|LATCH_OUT1[3] } { 0.000ns 0.000ns 2.400ns } { 0.000ns 4.900ns 0.800ns } } } } 0} } { { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "21.700 ns" { P2[1] mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "21.700 ns" { P2[1] P2[1]~out mcs_51:inst|process5~121 mcs_51:inst|process5~122 mcs_51:inst|WR_ENABLE1~65 mcs_51:inst|WR_ENABLE1~0 mcs_51:inst|LATCH_OUT1[3] } { 0.000ns 0.000ns 2.200ns 0.300ns 2.200ns 1.300ns 4.500ns } { 0.000ns 4.900ns 1.400ns 1.700ns 1.600ns 1.600ns 0.000ns } } } { "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" "" { Report "F:/EDA/mcs_51_cpld/db/mcs_51_cmp.qrpt" Compiler "mcs_51" "UNKNOWN" "V1" "F:/EDA/mcs_51_cpld/db/mcs_51.quartus_db" { Floorplan "F:/EDA/mcs_51_cpld/" "" "8.100 ns" { P0[3] P0~4 mcs_51:inst|LATCH_OUT1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.100 ns" { P0[3] P0~4 mcs_51:inst|LATCH_OUT1[3] } { 0.000ns 0.000ns 2.400ns } { 0.000ns 4.900ns 0.800ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 13 15:32:56 2005 " "Info: Processing ended: Sat Aug 13 15:32:56 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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