mcs_51.tan.qmsg

VHDL实现：单片机与FPGA接口通信源文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 13 15:32:55 2005 " "Info: Processing started: Sat Aug 13 15:32:55 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off mcs_51 -c mcs_51 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off mcs_51 -c mcs_51" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node \"ALE\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 144 -32 136 160 "ALE" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "LATCH1 " "Info: Assuming node \"LATCH1\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 192 -32 136 208 "LATCH1" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "LATCH1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[4\] " "Info: Assuming node \"P2\[4\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[4\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[6\] " "Info: Assuming node \"P2\[6\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[6\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[1\] " "Info: Assuming node \"P2\[1\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[1\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[0\] " "Info: Assuming node \"P2\[0\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[0\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[2\] " "Info: Assuming node \"P2\[2\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[2\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[3\] " "Info: Assuming node \"P2\[3\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[3\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 128 -32 136 144 "WR" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[7\] " "Info: Assuming node \"P2\[7\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[7\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P2\[5\] " "Info: Assuming node \"P2\[5\]\" is an undefined clock" {  } { { "MCS_51_CPLD.bdf" "" { Schematic "F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf" { { 96 -32 136 112 "P2\[7..0\]" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "P2\[5\]" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "16 " "Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|process5~123 " "Info: Detected gated clock \"mcs_51:inst\|process5~123\" as buffer" {  } { { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|process5~123" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|WR_ENABLE1~64 " "Info: Detected gated clock \"mcs_51:inst\|WR_ENABLE1~64\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|WR_ENABLE1~64" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|process5~121 " "Info: Detected gated clock \"mcs_51:inst\|process5~121\" as buffer" {  } { { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|process5~121" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|WR_ENABLE2~0 " "Info: Detected gated clock \"mcs_51:inst\|WR_ENABLE2~0\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 21 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|WR_ENABLE2~0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|WR_ENABLE1~65 " "Info: Detected gated clock \"mcs_51:inst\|WR_ENABLE1~65\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|WR_ENABLE1~65" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|WR_ENABLE1~63 " "Info: Detected gated clock \"mcs_51:inst\|WR_ENABLE1~63\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|WR_ENABLE1~63" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|WR_ENABLE1~0 " "Info: Detected gated clock \"mcs_51:inst\|WR_ENABLE1~0\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 20 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|WR_ENABLE1~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[4\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[4\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[7\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[7\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[7\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[0\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[0\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[1\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[1\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[2\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[2\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[3\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[3\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[3\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mcs_51:inst\|process5~122 " "Info: Detected gated clock \"mcs_51:inst\|process5~122\" as buffer" {  } { { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|process5~122" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[5\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[5\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "mcs_51:inst\|LATCH_ADDRES\[6\] " "Info: Detected ripple clock \"mcs_51:inst\|LATCH_ADDRES\[6\]\" as buffer" {  } { { "mcs_51.vhd" "" { Text "F:/EDA/mcs_51_cpld/mcs_51.vhd" 25 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "mcs_51:inst\|LATCH_ADDRES\[6\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ALE " "Info: No valid register-to-register data paths exist for clock \"ALE\"" {  } {  } 0}