mcs_51.hier_info

VHDL实现：单片机与FPGA接口通信源文件

|MCS_51_CPLD
AD_CS <= mcs_51:inst.AD_CS
RD => mcs_51:inst.RD
WR => mcs_51:inst.WR
ALE => mcs_51:inst.ALE
READY => mcs_51:inst.READY
LATCH1 => mcs_51:inst.LATCH1
DATAIN1[0] => mcs_51:inst.DATAIN1[0]
DATAIN1[1] => mcs_51:inst.DATAIN1[1]
DATAIN1[2] => mcs_51:inst.DATAIN1[2]
DATAIN1[3] => mcs_51:inst.DATAIN1[3]
DATAIN1[4] => mcs_51:inst.DATAIN1[4]
DATAIN1[5] => mcs_51:inst.DATAIN1[5]
DATAIN1[6] => mcs_51:inst.DATAIN1[6]
DATAIN1[7] => mcs_51:inst.DATAIN1[7]
P0[0] <= mcs_51:inst.P0[0]
P0[1] <= mcs_51:inst.P0[1]
P0[2] <= mcs_51:inst.P0[2]
P0[3] <= mcs_51:inst.P0[3]
P0[4] <= mcs_51:inst.P0[4]
P0[5] <= mcs_51:inst.P0[5]
P0[6] <= mcs_51:inst.P0[6]
P0[7] <= mcs_51:inst.P0[7]
P2[0] => mcs_51:inst.P2[0]
P2[1] => mcs_51:inst.P2[1]
P2[2] => mcs_51:inst.P2[2]
P2[3] => mcs_51:inst.P2[3]
P2[4] => mcs_51:inst.P2[4]
P2[5] => mcs_51:inst.P2[5]
P2[6] => mcs_51:inst.P2[6]
P2[7] => mcs_51:inst.P2[7]
DATAOUT1[0] <= mcs_51:inst.DATAOUT1[0]
DATAOUT1[1] <= mcs_51:inst.DATAOUT1[1]
DATAOUT1[2] <= mcs_51:inst.DATAOUT1[2]
DATAOUT1[3] <= mcs_51:inst.DATAOUT1[3]
DATAOUT1[4] <= mcs_51:inst.DATAOUT1[4]
DATAOUT1[5] <= mcs_51:inst.DATAOUT1[5]
DATAOUT1[6] <= mcs_51:inst.DATAOUT1[6]
DATAOUT1[7] <= mcs_51:inst.DATAOUT1[7]
DATAOUT2[0] <= mcs_51:inst.DATAOUT2[0]
DATAOUT2[1] <= mcs_51:inst.DATAOUT2[1]
DATAOUT2[2] <= mcs_51:inst.DATAOUT2[2]
DATAOUT2[3] <= mcs_51:inst.DATAOUT2[3]
DATAOUT2[4] <= mcs_51:inst.DATAOUT2[4]
DATAOUT2[5] <= mcs_51:inst.DATAOUT2[5]
DATAOUT2[6] <= mcs_51:inst.DATAOUT2[6]
DATAOUT2[7] <= mcs_51:inst.DATAOUT2[7]


|MCS_51_CPLD|mcs_51:inst
P0[0] <= process5~10
P0[1] <= process5~9
P0[2] <= process5~8
P0[3] <= process5~7
P0[4] <= process5~6
P0[5] <= process5~5
P0[6] <= process5~4
P0[7] <= process5~3
P2[0] => reduce_nor~5.IN4
P2[0] => reduce_nor~1.IN4
P2[0] => reduce_nor~3.IN4
P2[1] => reduce_nor~5.IN5
P2[1] => reduce_nor~1.IN5
P2[1] => reduce_nor~3.IN5
P2[2] => reduce_nor~5.IN6
P2[2] => reduce_nor~1.IN6
P2[2] => reduce_nor~3.IN6
P2[3] => reduce_nor~5.IN7
P2[3] => reduce_nor~1.IN7
P2[3] => reduce_nor~3.IN7
P2[4] => reduce_nor~1.IN1
P2[4] => reduce_nor~5.IN1
P2[4] => reduce_nor~3.IN1
P2[5] => reduce_nor~3.IN2
P2[5] => reduce_nor~5.IN2
P2[5] => reduce_nor~1.IN2
P2[6] => reduce_nor~3.IN3
P2[6] => reduce_nor~5.IN3
P2[6] => reduce_nor~1.IN3
P2[7] => reduce_nor~1.IN0
P2[7] => reduce_nor~3.IN0
P2[7] => reduce_nor~5.IN0
RD => process5~2.IN1
WR => WR_ENABLE1.DATAB
WR => WR_ENABLE2.DATAB
ALE => LATCH_ADDRES[6].CLK
ALE => LATCH_ADDRES[5].CLK
ALE => LATCH_ADDRES[4].CLK
ALE => LATCH_ADDRES[3].CLK
ALE => LATCH_ADDRES[2].CLK
ALE => LATCH_ADDRES[1].CLK
ALE => LATCH_ADDRES[0].CLK
ALE => LATCH_ADDRES[7].CLK
READY => process5~1.IN0
AD_CS <= reduce_nor~6.DB_MAX_OUTPUT_PORT_TYPE
DATAIN1[0] => LATCH_IN1[0].DATAIN
DATAIN1[1] => LATCH_IN1[1].DATAIN
DATAIN1[2] => LATCH_IN1[2].DATAIN
DATAIN1[3] => LATCH_IN1[3].DATAIN
DATAIN1[4] => LATCH_IN1[4].DATAIN
DATAIN1[5] => LATCH_IN1[5].DATAIN
DATAIN1[6] => LATCH_IN1[6].DATAIN
DATAIN1[7] => LATCH_IN1[7].DATAIN
LATCH1 => LATCH_IN1[6].CLK
LATCH1 => LATCH_IN1[5].CLK
LATCH1 => LATCH_IN1[4].CLK
LATCH1 => LATCH_IN1[3].CLK
LATCH1 => LATCH_IN1[2].CLK
LATCH1 => LATCH_IN1[1].CLK
LATCH1 => LATCH_IN1[0].CLK
LATCH1 => LATCH_IN1[7].CLK
DATAOUT1[0] <= LATCH_OUT1[0].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT1[1] <= LATCH_OUT1[1].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT1[2] <= LATCH_OUT1[2].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT1[3] <= LATCH_OUT1[3].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT1[4] <= LATCH_OUT1[4].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT1[5] <= LATCH_OUT1[5].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT1[6] <= LATCH_OUT1[6].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT1[7] <= LATCH_OUT1[7].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[0] <= LATCH_OUT2[0].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[1] <= LATCH_OUT2[1].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[2] <= LATCH_OUT2[2].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[3] <= LATCH_OUT2[3].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[4] <= LATCH_OUT2[4].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[5] <= LATCH_OUT2[5].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[6] <= LATCH_OUT2[6].DB_MAX_OUTPUT_PORT_TYPE
DATAOUT2[7] <= LATCH_OUT2[7].DB_MAX_OUTPUT_PORT_TYPE