mcs_51.map.eqn

VHDL实现：单片机与FPGA接口通信源文件

--B1_LATCH_ADDRES[6] is mcs_51:inst|LATCH_ADDRES[6]
--operation mode is normal

B1_LATCH_ADDRES[6]_lut_out = A1L14;
B1_LATCH_ADDRES[6] = DFFEA(B1_LATCH_ADDRES[6]_lut_out, !ALE, , , , , );


--B1_LATCH_ADDRES[5] is mcs_51:inst|LATCH_ADDRES[5]
--operation mode is normal

B1_LATCH_ADDRES[5]_lut_out = A1L24;
B1_LATCH_ADDRES[5] = DFFEA(B1_LATCH_ADDRES[5]_lut_out, !ALE, , , , , );


--B1_LATCH_ADDRES[3] is mcs_51:inst|LATCH_ADDRES[3]
--operation mode is normal

B1_LATCH_ADDRES[3]_lut_out = A1L44;
B1_LATCH_ADDRES[3] = DFFEA(B1_LATCH_ADDRES[3]_lut_out, !ALE, , , , , );


--B1_LATCH_ADDRES[2] is mcs_51:inst|LATCH_ADDRES[2]
--operation mode is normal

B1_LATCH_ADDRES[2]_lut_out = A1L54;
B1_LATCH_ADDRES[2] = DFFEA(B1_LATCH_ADDRES[2]_lut_out, !ALE, , , , , );


--B1_LATCH_ADDRES[1] is mcs_51:inst|LATCH_ADDRES[1]
--operation mode is normal

B1_LATCH_ADDRES[1]_lut_out = A1L64;
B1_LATCH_ADDRES[1] = DFFEA(B1_LATCH_ADDRES[1]_lut_out, !ALE, , , , , );


--B1_LATCH_ADDRES[0] is mcs_51:inst|LATCH_ADDRES[0]
--operation mode is normal

B1_LATCH_ADDRES[0]_lut_out = A1L74;
B1_LATCH_ADDRES[0] = DFFEA(B1_LATCH_ADDRES[0]_lut_out, !ALE, , , , , );


--B1L93 is mcs_51:inst|process5~119
--operation mode is normal

B1L93 = B1_LATCH_ADDRES[1] & !B1_LATCH_ADDRES[0];


--B1_LATCH_ADDRES[7] is mcs_51:inst|LATCH_ADDRES[7]
--operation mode is normal

B1_LATCH_ADDRES[7]_lut_out = A1L04;
B1_LATCH_ADDRES[7] = DFFEA(B1_LATCH_ADDRES[7]_lut_out, !ALE, , , , , );


--B1L04 is mcs_51:inst|process5~120
--operation mode is normal

B1L04 = B1_LATCH_ADDRES[3] & B1_LATCH_ADDRES[2] & B1L93 & !B1_LATCH_ADDRES[7];


--B1_LATCH_ADDRES[4] is mcs_51:inst|LATCH_ADDRES[4]
--operation mode is normal

B1_LATCH_ADDRES[4]_lut_out = A1L34;
B1_LATCH_ADDRES[4] = DFFEA(B1_LATCH_ADDRES[4]_lut_out, !ALE, , , , , );


--B1_AD_CS is mcs_51:inst|AD_CS
--operation mode is normal

B1_AD_CS = B1_LATCH_ADDRES[6] # B1_LATCH_ADDRES[5] # !B1_LATCH_ADDRES[4] # !B1L04;


--B1_LATCH_OUT1[7] is mcs_51:inst|LATCH_OUT1[7]
--operation mode is normal

B1_LATCH_OUT1[7]_lut_out = A1L04;
B1_LATCH_OUT1[7] = DFFEA(B1_LATCH_OUT1[7]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT1[6] is mcs_51:inst|LATCH_OUT1[6]
--operation mode is normal

B1_LATCH_OUT1[6]_lut_out = A1L14;
B1_LATCH_OUT1[6] = DFFEA(B1_LATCH_OUT1[6]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT1[5] is mcs_51:inst|LATCH_OUT1[5]
--operation mode is normal

B1_LATCH_OUT1[5]_lut_out = A1L24;
B1_LATCH_OUT1[5] = DFFEA(B1_LATCH_OUT1[5]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT1[4] is mcs_51:inst|LATCH_OUT1[4]
--operation mode is normal

B1_LATCH_OUT1[4]_lut_out = A1L34;
B1_LATCH_OUT1[4] = DFFEA(B1_LATCH_OUT1[4]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT1[3] is mcs_51:inst|LATCH_OUT1[3]
--operation mode is normal

B1_LATCH_OUT1[3]_lut_out = A1L44;
B1_LATCH_OUT1[3] = DFFEA(B1_LATCH_OUT1[3]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT1[2] is mcs_51:inst|LATCH_OUT1[2]
--operation mode is normal

B1_LATCH_OUT1[2]_lut_out = A1L54;
B1_LATCH_OUT1[2] = DFFEA(B1_LATCH_OUT1[2]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT1[1] is mcs_51:inst|LATCH_OUT1[1]
--operation mode is normal

B1_LATCH_OUT1[1]_lut_out = A1L64;
B1_LATCH_OUT1[1] = DFFEA(B1_LATCH_OUT1[1]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT1[0] is mcs_51:inst|LATCH_OUT1[0]
--operation mode is normal

B1_LATCH_OUT1[0]_lut_out = A1L74;
B1_LATCH_OUT1[0] = DFFEA(B1_LATCH_OUT1[0]_lut_out, B1L54, , , , , );


--B1_LATCH_OUT2[7] is mcs_51:inst|LATCH_OUT2[7]
--operation mode is normal

B1_LATCH_OUT2[7]_lut_out = A1L04;
B1_LATCH_OUT2[7] = DFFEA(B1_LATCH_OUT2[7]_lut_out, B1L94, , , , , );


--B1_LATCH_OUT2[6] is mcs_51:inst|LATCH_OUT2[6]
--operation mode is normal

B1_LATCH_OUT2[6]_lut_out = A1L14;
B1_LATCH_OUT2[6] = DFFEA(B1_LATCH_OUT2[6]_lut_out, B1L94, , , , , );


--B1_LATCH_OUT2[5] is mcs_51:inst|LATCH_OUT2[5]
--operation mode is normal

B1_LATCH_OUT2[5]_lut_out = A1L24;
B1_LATCH_OUT2[5] = DFFEA(B1_LATCH_OUT2[5]_lut_out, B1L94, , , , , );


--B1_LATCH_OUT2[4] is mcs_51:inst|LATCH_OUT2[4]
--operation mode is normal

B1_LATCH_OUT2[4]_lut_out = A1L34;
B1_LATCH_OUT2[4] = DFFEA(B1_LATCH_OUT2[4]_lut_out, B1L94, , , , , );


--B1_LATCH_OUT2[3] is mcs_51:inst|LATCH_OUT2[3]
--operation mode is normal

B1_LATCH_OUT2[3]_lut_out = A1L44;
B1_LATCH_OUT2[3] = DFFEA(B1_LATCH_OUT2[3]_lut_out, B1L94, , , , , );


--B1_LATCH_OUT2[2] is mcs_51:inst|LATCH_OUT2[2]
--operation mode is normal

B1_LATCH_OUT2[2]_lut_out = A1L54;
B1_LATCH_OUT2[2] = DFFEA(B1_LATCH_OUT2[2]_lut_out, B1L94, , , , , );


--B1_LATCH_OUT2[1] is mcs_51:inst|LATCH_OUT2[1]
--operation mode is normal

B1_LATCH_OUT2[1]_lut_out = A1L64;
B1_LATCH_OUT2[1] = DFFEA(B1_LATCH_OUT2[1]_lut_out, B1L94, , , , , );


--B1_LATCH_OUT2[0] is mcs_51:inst|LATCH_OUT2[0]
--operation mode is normal

B1_LATCH_OUT2[0]_lut_out = A1L74;
B1_LATCH_OUT2[0] = DFFEA(B1_LATCH_OUT2[0]_lut_out, B1L94, , , , , );


--B1L64 is mcs_51:inst|WR_ENABLE1~63
--operation mode is normal

B1L64 = B1_LATCH_ADDRES[1] # P2[4] # !P2[6] # !B1_LATCH_ADDRES[2];


--B1L14 is mcs_51:inst|process5~121
--operation mode is normal

B1L14 = B1_LATCH_ADDRES[6] & B1_LATCH_ADDRES[5] & B1_LATCH_ADDRES[4] & P2[1];


--B1L24 is mcs_51:inst|process5~122
--operation mode is normal

B1L24 = B1L14 & P2[0] & P2[2] & P2[3];


--B1L74 is mcs_51:inst|WR_ENABLE1~64
--operation mode is normal

B1L74 = B1_LATCH_ADDRES[0] & B1_LATCH_ADDRES[7] & !B1_LATCH_ADDRES[3] & !WR;


--B1L84 is mcs_51:inst|WR_ENABLE1~65
--operation mode is normal

B1L84 = B1L24 & B1L74 & !P2[7];


--B1L54 is mcs_51:inst|WR_ENABLE1~0
--operation mode is normal

B1L54 = B1L64 # !P2[5] # !B1L84;


--B1L34 is mcs_51:inst|process5~123
--operation mode is normal

B1L34 = P2[4] & !P2[6] & !P2[5];


--B1L94 is mcs_51:inst|WR_ENABLE2~0
--operation mode is normal

B1L94 = B1_LATCH_ADDRES[2] # !B1L34 # !B1_LATCH_ADDRES[1] # !B1L84;


--B1_LATCH_IN1[7] is mcs_51:inst|LATCH_IN1[7]
--operation mode is normal

B1_LATCH_IN1[7]_lut_out = DATAIN1[7];
B1_LATCH_IN1[7] = DFFEA(B1_LATCH_IN1[7]_lut_out, LATCH1, , , , , );


--B1L44 is mcs_51:inst|process5~124
--operation mode is normal

B1L44 = P2[7] & B1L34 & READY & !RD;


--B1L83 is mcs_51:inst|process5~2
--operation mode is normal

B1L83 = B1L04 & B1L24 & B1L44;


--B1_LATCH_IN1[6] is mcs_51:inst|LATCH_IN1[6]
--operation mode is normal

B1_LATCH_IN1[6]_lut_out = DATAIN1[6];
B1_LATCH_IN1[6] = DFFEA(B1_LATCH_IN1[6]_lut_out, LATCH1, , , , , );


--B1_LATCH_IN1[5] is mcs_51:inst|LATCH_IN1[5]
--operation mode is normal

B1_LATCH_IN1[5]_lut_out = DATAIN1[5];
B1_LATCH_IN1[5] = DFFEA(B1_LATCH_IN1[5]_lut_out, LATCH1, , , , , );


--B1_LATCH_IN1[4] is mcs_51:inst|LATCH_IN1[4]
--operation mode is normal

B1_LATCH_IN1[4]_lut_out = DATAIN1[4];
B1_LATCH_IN1[4] = DFFEA(B1_LATCH_IN1[4]_lut_out, LATCH1, , , , , );


--B1_LATCH_IN1[3] is mcs_51:inst|LATCH_IN1[3]
--operation mode is normal

B1_LATCH_IN1[3]_lut_out = DATAIN1[3];
B1_LATCH_IN1[3] = DFFEA(B1_LATCH_IN1[3]_lut_out, LATCH1, , , , , );


--B1_LATCH_IN1[2] is mcs_51:inst|LATCH_IN1[2]
--operation mode is normal

B1_LATCH_IN1[2]_lut_out = DATAIN1[2];
B1_LATCH_IN1[2] = DFFEA(B1_LATCH_IN1[2]_lut_out, LATCH1, , , , , );


--B1_LATCH_IN1[1] is mcs_51:inst|LATCH_IN1[1]
--operation mode is normal

B1_LATCH_IN1[1]_lut_out = DATAIN1[1];
B1_LATCH_IN1[1] = DFFEA(B1_LATCH_IN1[1]_lut_out, LATCH1, , , , , );


--B1_LATCH_IN1[0] is mcs_51:inst|LATCH_IN1[0]
--operation mode is normal

B1_LATCH_IN1[0]_lut_out = DATAIN1[0];
B1_LATCH_IN1[0] = DFFEA(B1_LATCH_IN1[0]_lut_out, LATCH1, , , , , );


--ALE is ALE
--operation mode is input

ALE = INPUT();


--P2[4] is P2[4]
--operation mode is input

P2[4] = INPUT();


--P2[6] is P2[6]
--operation mode is input

P2[6] = INPUT();


--P2[1] is P2[1]
--operation mode is input

P2[1] = INPUT();


--P2[0] is P2[0]
--operation mode is input

P2[0] = INPUT();


--P2[2] is P2[2]
--operation mode is input

P2[2] = INPUT();


--P2[3] is P2[3]
--operation mode is input

P2[3] = INPUT();


--WR is WR
--operation mode is input

WR = INPUT();


--P2[7] is P2[7]
--operation mode is input

P2[7] = INPUT();


--P2[5] is P2[5]
--operation mode is input

P2[5] = INPUT();


--READY is READY
--operation mode is input

READY = INPUT();


--RD is RD
--operation mode is input

RD = INPUT();


--DATAIN1[7] is DATAIN1[7]
--operation mode is input

DATAIN1[7] = INPUT();


--LATCH1 is LATCH1
--operation mode is input

LATCH1 = INPUT();


--DATAIN1[6] is DATAIN1[6]
--operation mode is input

DATAIN1[6] = INPUT();


--DATAIN1[5] is DATAIN1[5]
--operation mode is input

DATAIN1[5] = INPUT();


--DATAIN1[4] is DATAIN1[4]
--operation mode is input

DATAIN1[4] = INPUT();


--DATAIN1[3] is DATAIN1[3]
--operation mode is input

DATAIN1[3] = INPUT();


--DATAIN1[2] is DATAIN1[2]
--operation mode is input

DATAIN1[2] = INPUT();


--DATAIN1[1] is DATAIN1[1]
--operation mode is input

DATAIN1[1] = INPUT();


--DATAIN1[0] is DATAIN1[0]
--operation mode is input

DATAIN1[0] = INPUT();


--AD_CS is AD_CS
--operation mode is output

AD_CS = OUTPUT(B1_AD_CS);


--DATAOUT1[7] is DATAOUT1[7]
--operation mode is output

DATAOUT1[7] = OUTPUT(B1_LATCH_OUT1[7]);


--DATAOUT1[6] is DATAOUT1[6]
--operation mode is output

DATAOUT1[6] = OUTPUT(B1_LATCH_OUT1[6]);


--DATAOUT1[5] is DATAOUT1[5]
--operation mode is output

DATAOUT1[5] = OUTPUT(B1_LATCH_OUT1[5]);


--DATAOUT1[4] is DATAOUT1[4]
--operation mode is output

DATAOUT1[4] = OUTPUT(B1_LATCH_OUT1[4]);


--DATAOUT1[3] is DATAOUT1[3]
--operation mode is output

DATAOUT1[3] = OUTPUT(B1_LATCH_OUT1[3]);


--DATAOUT1[2] is DATAOUT1[2]
--operation mode is output

DATAOUT1[2] = OUTPUT(B1_LATCH_OUT1[2]);


--DATAOUT1[1] is DATAOUT1[1]
--operation mode is output

DATAOUT1[1] = OUTPUT(B1_LATCH_OUT1[1]);


--DATAOUT1[0] is DATAOUT1[0]
--operation mode is output

DATAOUT1[0] = OUTPUT(B1_LATCH_OUT1[0]);


--DATAOUT2[7] is DATAOUT2[7]
--operation mode is output

DATAOUT2[7] = OUTPUT(B1_LATCH_OUT2[7]);


--DATAOUT2[6] is DATAOUT2[6]
--operation mode is output

DATAOUT2[6] = OUTPUT(B1_LATCH_OUT2[6]);


--DATAOUT2[5] is DATAOUT2[5]
--operation mode is output

DATAOUT2[5] = OUTPUT(B1_LATCH_OUT2[5]);


--DATAOUT2[4] is DATAOUT2[4]
--operation mode is output

DATAOUT2[4] = OUTPUT(B1_LATCH_OUT2[4]);


--DATAOUT2[3] is DATAOUT2[3]
--operation mode is output

DATAOUT2[3] = OUTPUT(B1_LATCH_OUT2[3]);


--DATAOUT2[2] is DATAOUT2[2]
--operation mode is output

DATAOUT2[2] = OUTPUT(B1_LATCH_OUT2[2]);


--DATAOUT2[1] is DATAOUT2[1]
--operation mode is output

DATAOUT2[1] = OUTPUT(B1_LATCH_OUT2[1]);


--DATAOUT2[0] is DATAOUT2[0]
--operation mode is output

DATAOUT2[0] = OUTPUT(B1_LATCH_OUT2[0]);


--A1L04 is P0~0
--operation mode is bidir

A1L04 = P0[7];

--P0[7] is P0[7]
--operation mode is bidir

P0[7]_tri_out = TRI(B1_LATCH_IN1[7], B1L83);
P0[7] = BIDIR(P0[7]_tri_out);


--A1L14 is P0~1
--operation mode is bidir

A1L14 = P0[6];

--P0[6] is P0[6]
--operation mode is bidir

P0[6]_tri_out = TRI(B1_LATCH_IN1[6], B1L83);
P0[6] = BIDIR(P0[6]_tri_out);


--A1L24 is P0~2
--operation mode is bidir

A1L24 = P0[5];

--P0[5] is P0[5]
--operation mode is bidir

P0[5]_tri_out = TRI(B1_LATCH_IN1[5], B1L83);
P0[5] = BIDIR(P0[5]_tri_out);


--A1L34 is P0~3
--operation mode is bidir

A1L34 = P0[4];

--P0[4] is P0[4]
--operation mode is bidir

P0[4]_tri_out = TRI(B1_LATCH_IN1[4], B1L83);
P0[4] = BIDIR(P0[4]_tri_out);


--A1L44 is P0~4
--operation mode is bidir

A1L44 = P0[3];

--P0[3] is P0[3]
--operation mode is bidir

P0[3]_tri_out = TRI(B1_LATCH_IN1[3], B1L83);
P0[3] = BIDIR(P0[3]_tri_out);


--A1L54 is P0~5
--operation mode is bidir

A1L54 = P0[2];

--P0[2] is P0[2]
--operation mode is bidir

P0[2]_tri_out = TRI(B1_LATCH_IN1[2], B1L83);
P0[2] = BIDIR(P0[2]_tri_out);


--A1L64 is P0~6
--operation mode is bidir

A1L64 = P0[1];

--P0[1] is P0[1]
--operation mode is bidir

P0[1]_tri_out = TRI(B1_LATCH_IN1[1], B1L83);
P0[1] = BIDIR(P0[1]_tri_out);


--A1L74 is P0~7
--operation mode is bidir

A1L74 = P0[0];

--P0[0] is P0[0]
--operation mode is bidir

P0[0]_tri_out = TRI(B1_LATCH_IN1[0], B1L83);
P0[0] = BIDIR(P0[0]_tri_out);