mcs_51.vhd

VHDL实现：单片机与FPGA接口通信源文件

library ieee;
use ieee.std_logic_1164.all;
entity mcs_51 is
   port(P0:inout std_logic_vector(7 downto 0); --双向地址数据口
        P2:in std_logic_vector(7 downto 0);--高八位地址线
         RD,WR:IN STD_LOGIC;--读、写允许
          ALE:IN STD_LOGIC;--地址锁存
          READY:IN STD_LOGIC;--待读入数据准备就绪标志位	
          AD_CS:OUT STD_LOGIC;--A/D器件片选信号
     DATAIN1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);--单片机待读回信号
      LATCH1:IN STD_LOGIC;--读回信号锁存
      DATAOUT1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--锁存输出数据1
     DATAOUT2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--锁存输出数据2
END;
ARCHITECTURE ART OF mcs_51 IS
 SIGNAL LATCH_ADDRES:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LATCH_OUT1:STD_LOGIC_VECTOR(7 DOWNTO 0);
 SIGNAL LATCH_OUT2:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LATCH_IN1:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL WR_ENABLE1:STD_LOGIC;
SIGNAL WR_ENABLE2:STD_LOGIC;
BEGIN
  PROCESS(ALE) IS
        BEGIN
            IF ALE'EVENT AND ALE='0' THEN
            LATCH_ADDRES<=P0;
         END IF;
 END PROCESS;
PROCESS(P2,LATCH_ADDRES) IS
  BEGIN
        IF(LATCH_ADDRES="11110101") AND (P2="01101111") THEN
          WR_ENABLE1<=WR;
     ELSE WR_ENABLE1<='1';
 END IF;
END PROCESS;

PROCESS(WR_ENABLE1) IS
  BEGIN
IF WR_ENABLE1'EVENT AND WR_ENABLE1='1' THEN
           LATCH_OUT1<=P0;
       END IF;
END PROCESS;

PROCESS(P2,LATCH_ADDRES) IS
     BEGIN
         IF(LATCH_ADDRES="11110011") AND (P2="00011111") THEN
           WR_ENABLE2<=WR;
         ELSE WR_ENABLE2<='1';
    END IF;
END PROCESS;

PROCESS(WR_ENABLE2)IS
    BEGIN
  IF WR_ENABLE2'EVENT AND WR_ENABLE2='1' THEN
        LATCH_OUT2<=P0;
       END IF;
END PROCESS;

PROCESS(P2,LATCH_ADDRES,READY,RD) IS
           BEGIN
       IF(LATCH_ADDRES="01111110") AND (P2="10011111") AND (READY='1')
          AND(RD='0') THEN
            P0<=LATCH_IN1;
       ELSE P0<="ZZZZZZZZ"; END IF;
END PROCESS;

PROCESS(LATCH1) IS
 BEGIN
   IF LATCH1'EVENT AND LATCH1='1' THEN
  LATCH_IN1<=DATAIN1;
 END IF;
END PROCESS;

PROCESS(LATCH_ADDRES) IS
  BEGIN
 IF(LATCH_ADDRES="00011110") THEN 
           AD_CS<='0';
        ELSE AD_CS<='1' ;
 END IF;
END PROCESS;

DATAOUT1<=LATCH_OUT1;DATAOUT2<=LATCH_OUT2;
END ;