📄 mcs_51.map.rpt
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Analysis & Synthesis report for mcs_51
Sat Aug 13 15:32:41 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Hierarchy
5. Analysis & Synthesis Resource Utilization by Entity
6. Analysis & Synthesis Equations
7. Analysis & Synthesis Source Files Read
8. Analysis & Synthesis Resource Usage Summary
9. WYSIWYG Cells
10. General Register Statistics
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Aug 13 15:32:41 2005 ;
; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name ; mcs_51 ;
; Top-level Entity Name ; MCS_51_CPLD ;
; Family ; ACEX1K ;
; Total logic elements ; 45 ;
; Total pins ; 46 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------+---------------+---------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------+---------------+---------------+
; Device ; EP1K30TC144-3 ; ;
; Family name ; ACEX1K ; Stratix ;
; Top-level entity name ; MCS_51_CPLD ; mcs_51 ;
; Use smart compilation ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
+------------------------------------------------------+---------------+---------------+
+-----------+
; Hierarchy ;
+-----------+
MCS_51_CPLD
|-- mcs_51:inst
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------+
; |MCS_51_CPLD ; 45 (0) ; 32 ; 0 ; 46 ; 13 (0) ; 32 (0) ; 0 (0) ; 0 (0) ; |MCS_51_CPLD ;
; |mcs_51:inst| ; 45 (45) ; 32 ; 0 ; 0 ; 13 (13) ; 32 (32) ; 0 (0) ; 0 (0) ; |MCS_51_CPLD|mcs_51:inst ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/EDA/mcs_51_cpld/mcs_51.map.eqn.
+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+
; mcs_51.vhd ; yes ; F:/EDA/mcs_51_cpld/mcs_51.vhd ;
; MCS_51_CPLD.bdf ; yes ; F:/EDA/mcs_51_cpld/MCS_51_CPLD.bdf ;
+----------------------------------+-----------------+------------------------------------+
+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------+--------------------------+
; Logic cells ; 45 ;
; Total combinational functions ; 13 ;
; Total 4-input functions ; 8 ;
; Total 3-input functions ; 4 ;
; Total 2-input functions ; 1 ;
; Total 1-input functions ; 0 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 32 ;
; I/O pins ; 46 ;
; Maximum fan-out node ; mcs_51:inst|WR_ENABLE1~0 ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 143 ;
; Average fan-out ; 1.57 ;
+---------------------------------+--------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 0 ;
; Number of synthesis-generated cells ; 45 ;
; Number of WYSIWYG LUTs ; 0 ;
; Number of synthesis-generated LUTs ; 13 ;
; Number of WYSIWYG registers ; 0 ;
; Number of synthesis-generated registers ; 32 ;
; Number of cells with combinational logic only ; 13 ;
; Number of cells with registers only ; 32 ;
; Number of cells with combinational logic and registers ; 0 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 32 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Sat Aug 13 15:32:38 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off mcs_51 -c mcs_51
Info: Found 2 design units, including 1 entities, in source file mcs_51.vhd
Info: Found design unit 1: mcs_51-ART
Info: Found entity 1: mcs_51
Info: Found 1 design units, including 1 entities, in source file MCS_51_CPLD.bdf
Info: Found entity 1: MCS_51_CPLD
Warning: VHDL Process Statement warning at mcs_51.vhd(32): signal "WR" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at mcs_51.vhd(47): signal "WR" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at mcs_51.vhd(63): signal "LATCH_IN1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 91 device resources after synthesis - the final resource count might be different
Info: Implemented 21 input pins
Info: Implemented 17 output pins
Info: Implemented 8 bidirectional pins
Info: Implemented 45 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Processing ended: Sat Aug 13 15:32:41 2005
Info: Elapsed time: 00:00:03
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