grp400s_reg.h

TEA5761是目前飞利浦比较先进的FM芯片

#ifndef __GRP400S_REG_H__
#define __GRP400S_REG_H__

//W00
typedef union {
	U8	REGW;
	struct {
		U8	BLMSK		:1;
	    U8	FRMSK		:1;
		U8	LEVMSK		:1;
	    U8	IFMSK		:1;
		U8	REV			:4;
	} REGWB;
} INTREGW;

//W01
typedef union {
	U8	REGW;
	struct {
		U8	FR_H		:6;
	    U8	SM			:1;
		U8	SUD			:1;
	} REGWB;
} FREQSETW0;

//W02
typedef union {
	U8	REGW;
	struct {
		U8	FR_L		:8;
	} REGWB;
} FREQSETW1;

//W03
typedef union {
	U8	REGW;
	struct {
		U8	SNC			:1;
		U8	SMUTE		:1;
		U8	AFM			:1;
		U8	IFCTC		:1;
		U8	SWPM		:1;
		U8	BLIM		:1;
		U8	PUPD_0		:1;
		U8	REV			:1;
	} REGWB;
} TNCTRLW0;

//W04
typedef union {
	U8	REGW;
	struct {
		U8	AHLSI		:1;
		U8	DTC			:1;
		U8	SWP			:1;
		U8	MST			:1;
		U8	HLSI		:1;
		U8	SSL_0		:1;
		U8	SSL_1		:1;
		U8	MU			:1;
	} REGWB;
} TNCTRLW1;

//W05
typedef union {
	U8	REGW;
	struct {
		U8	INTCTRL		:1;
		U8	RFAGC		:1;
		U8	LDX			:1;
		U8	TRIGFR		:1;
		U8	LHSW		:1;
		U8	REV			:1;
		U8	RHM			:1;
		U8	LHM			:1;
	} REGWB;
} TESTREGW0;

//W06
typedef union {
	U8	REGW;
	struct {
		U8	TB			:5;
		U8	REV			:2;
		U8	DETT		:1;
	} REGWB;
} TESTREGW1;

//W00~W06
typedef	union {
	U8	REGW[7];
	struct	{
		INTREGW		intreg;
		FREQSETW0	freqseth;
		FREQSETW1	freqsetl;
		TNCTRLW0	tnctrlh;
		TNCTRLW1	tnctrll;
		TESTREGW0	testregh;
		TESTREGW1	testregl;
	} register_map;
} RADIO_WRITE_REGISTER;

/*---------------------------------------------------------------*/
//	RADIO READ STRUCTURE
/*---------------------------------------------------------------*/
//R00
typedef union {
	U8	REGR;
	struct {
		U8	BLFLAG		:1;
	    U8	FRRFLAG		:1;
		U8	LEVFLAG		:1;
	    U8	IFMSK		:1;
		U8	REV			:4;
	} REGRB;
} INTREGR0;

//R01
typedef union {
	U8	REGR;
	struct {
		U8	BLMSK		:1;
	    U8	FRMSK		:1;
		U8	LEVMSK		:1;
	    U8	IFMSK		:1;
		U8	REV			:4;
	} REGRB;
} INTREGR1;

//R02
typedef union {
	U8	REGR;
	struct {
		U8	FR_H		:6;
	    U8	SM			:1;
		U8	SUD			:1;
	} REGRB;
} FREQSETR0;

//R03
typedef union {
	U8	REGR;
	struct {
		U8	FR_L		:8;
	} REGRB;
} FREQSETR1;

//R04
typedef union {
	U8	REGR;
	struct {
		U8	SNC			:1;
		U8	SMUTE		:1;
		U8	AFM			:1;
		U8	IFCTC		:1;
		U8	SWPM		:1;
		U8	BLIM		:1;
		U8	PUPD_0		:1;
		U8	REV			:1;
	} REGRB;
} TNCTRLR0;

//R05
typedef union {
	U8	REGR;
	struct {
		U8	AHLSI		:1;
		U8	DTC			:1;
		U8	SWP			:1;
		U8	MST			:1;
		U8	HLSI		:1;
		U8	SSL_0		:1;
		U8	SSL_1		:1;
		U8	MU			:1;
	} REGRB;
} TNCTRLR1;

//R06
typedef union {
	U8	REGR;
	struct {
		U8	PLL_H		:6;
		U8	REV			:2;
	} REGRB;
} FRQCHKR0;

//R07
typedef union {
	U8	REGR;
	struct {
		U8	PLL_L		:8;
	} REGRB;
} FRQCHKR1;

//R08
typedef union {
	U8	REGR;
	struct {
		U8	TUNTO		:1;
		U8	IF			:7;
	} REGRB;
} TUNCHKR0;

//R09
typedef union {
	U8	REGR;
	struct {
		U8	REV			:2;
		U8	STEREO		:1;
		U8	LD			:1;
		U8	LEV			:4;
	} REGRB;
} TUNCHKR1;

//R10
typedef union {
	U8	REGR;
	struct {
		U8	INTCTRL		:1;
		U8	RFAGC		:1;
		U8	LDX			:1;
		U8	TRIGFR		:1;
		U8	LHSW		:1;
		U8	REV			:1;
		U8	RHM			:1;
		U8	LHM			:1;
	} REGRB;
} TESTREGR0;

//R11
typedef union {
	U8	REGR;
	struct {
		U8	TB			:5;
		U8	REV			:2;
		U8	DETT		:1;
	} REGRB;
} TESTREGR1;

//R12
typedef union {
	U8	REGR;
	struct {
		U8	MANID_H		:4;
		U8	VERSION		:4;
	} REGRB;
} MANIDR0;

//R13
typedef union {
	U8	REGR;
	struct {
		U8	IDAV		:1;
		U8	MANID_L		:7;
	} REGRB;
} MANIDR1;

//R14
typedef union {
	U8	REGR;
	struct {
		U8	CHIPID_H	:8;
	} REGRB;
} CHIPIDR0;

//R15
typedef union {
	U8	REGR;
	struct {
		U8	CHIPID_L	:8;
	} REGRB;
} CHIPIDR1;

//R00~R15
typedef union {
	U8 REGR[16];
	struct	{
		INTREGR0	intregh;
		INTREGR1	intregl;
		FREQSETR0	freqseth;
		FREQSETR1	freqsetl;
		TNCTRLR0	tnctrlh;
		TNCTRLR1	tnctrll;
		FRQCHKR0	freqchkh;
		FRQCHKR1	freqchkl;
		TUNCHKR0	tunchkh;
		TUNCHKR1	tunchkl;
		TESTREGR0	testregh;
		TESTREGR1	testregl;
		MANIDR0		manidh;
		MANIDR1		manidl;
		CHIPIDR0	chipidh;
		CHIPIDR1	chipidl;
	} register_map;
} RADIO_READ_REGISTER;

#endif