tlc7524.vhd

来自「CPLD下的A/D转换器TCL5510驱动源码」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tlc7524 is
         port(clk: in std_logic;                          --系统时钟
              rst: in std_logic;                          --复位信号
              data_out: out std_logic_vector(7 downto 0));  --待转换数据
       end tlc7524;
architecture behav of tlc7524 is
       signal b:integer range 0 to 63;       --地址记数器
       signal q:integer range  0 to 4;       --记数器
       signal d:integer range  0 to 255;    --数据寄存器，使用时可自行定义
     begin
        process(clk)
           begin
           if rst'event and b<=0;
           elsif clk'event and clk='1' then
                if q=4 then q<=0;
                 if b=63 then b<=0;
                 else b<=b+1;
                 end if;
                else q<=q+1;
                end if;
           end if;
       end process;
process(b)
    begin
      case b is
          when 00=>d<=255;                       --此处定义寄存器的数据
      end case
  end process;
     data_out<=conv_std_logic_vector(d,8);
 end behav;