📄 tlc5510.rpt
字号:
- 2 - C 04 LCELL s 1 0 1 0 dout3~1
- 8 - B 12 LCELL s 1 0 1 0 dout4~1
- 4 - B 05 LCELL s 1 0 1 0 dout5~1
- 7 - A 06 LCELL s 1 0 1 0 dout6~1
- 2 - C 18 LCELL s 1 0 1 0 dout7~1
- 2 - B 04 DFFE + 0 1 1 0 :3
- 3 - B 04 DFFE + 0 1 0 1 q1 (:21)
- 1 - B 04 DFFE + 0 0 0 1 q0 (:22)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\cpld-fpga\tlc5510\tlc5510.rpt
tlc5510
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 2/ 48( 4%) 1/ 48( 2%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 4/ 96( 4%) 1/ 48( 2%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
C: 1/ 96( 1%) 1/ 48( 2%) 1/ 48( 2%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cpld-fpga\tlc5510\tlc5510.rpt
tlc5510
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clk
Device-Specific Information: e:\cpld-fpga\tlc5510\tlc5510.rpt
tlc5510
** EQUATIONS **
clk : INPUT;
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
din4 : INPUT;
din5 : INPUT;
din6 : INPUT;
din7 : INPUT;
-- Node name is 'clk1'
-- Equation name is 'clk1', type is output
clk1 = _LC2_B4;
-- Node name is 'dout0~1'
-- Equation name is 'dout0~1', location is LC5_A13, type is buried.
-- synthesized logic cell
_LC5_A13 = LCELL( din0);
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC5_A13;
-- Node name is 'dout1~1'
-- Equation name is 'dout1~1', location is LC6_B6, type is buried.
-- synthesized logic cell
_LC6_B6 = LCELL( din1);
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC6_B6;
-- Node name is 'dout2~1'
-- Equation name is 'dout2~1', location is LC2_A10, type is buried.
-- synthesized logic cell
_LC2_A10 = LCELL( din2);
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC2_A10;
-- Node name is 'dout3~1'
-- Equation name is 'dout3~1', location is LC2_C4, type is buried.
-- synthesized logic cell
_LC2_C4 = LCELL( din3);
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC2_C4;
-- Node name is 'dout4~1'
-- Equation name is 'dout4~1', location is LC8_B12, type is buried.
-- synthesized logic cell
_LC8_B12 = LCELL( din4);
-- Node name is 'dout4'
-- Equation name is 'dout4', type is output
dout4 = _LC8_B12;
-- Node name is 'dout5~1'
-- Equation name is 'dout5~1', location is LC4_B5, type is buried.
-- synthesized logic cell
_LC4_B5 = LCELL( din5);
-- Node name is 'dout5'
-- Equation name is 'dout5', type is output
dout5 = _LC4_B5;
-- Node name is 'dout6~1'
-- Equation name is 'dout6~1', location is LC7_A6, type is buried.
-- synthesized logic cell
_LC7_A6 = LCELL( din6);
-- Node name is 'dout6'
-- Equation name is 'dout6', type is output
dout6 = _LC7_A6;
-- Node name is 'dout7~1'
-- Equation name is 'dout7~1', location is LC2_C18, type is buried.
-- synthesized logic cell
_LC2_C18 = LCELL( din7);
-- Node name is 'dout7'
-- Equation name is 'dout7', type is output
dout7 = _LC2_C18;
-- Node name is 'oe'
-- Equation name is 'oe', type is output
oe = GND;
-- Node name is ':22' = 'q0'
-- Equation name is 'q0', location is LC1_B4, type is buried.
q0 = DFFE(!q0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':21' = 'q1'
-- Equation name is 'q1', location is LC3_B4, type is buried.
q1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !q0 & q1
# q0 & !q1;
-- Node name is ':3'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = DFFE( q1, GLOBAL( clk), VCC, VCC, VCC);
Project Information e:\cpld-fpga\tlc5510\tlc5510.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,672K
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