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来自「cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言」· 代码 · 共 42 行

// counter
module cc1(clk,out);
input clk;
output [7:0] out;
reg [19:0] ddd;
reg [7:0] out;

always @(posedge clk) begin
  if (ddd==999999) ddd<=0;
  else ddd<=ddd+1;
end

reg [3:0] in;
always @(posedge clk) begin 
 if (ddd==0) in<=in+1;
end

always begin
	      case (in)
		          4'b0000: out = ~8'b00000001;
		          4'b0001: out = ~8'b00000010;
		          4'b0010: out = ~8'b00000100;
		          4'b0011: out = ~8'b00001000;
				  4'b0100: out = ~8'b00010000;
				  4'b0101: out = ~8'b00100000;
		          4'b0110: out = ~8'b01000000;
		          4'b0111: out = ~8'b10000000;
		          4'b1000: out = ~8'b10000000;
		          4'b1001: out = ~8'b01000000;
		          4'b1010: out = ~8'b00100000;
		          4'b1011: out = ~8'b00010000;
				  4'b1100: out = ~8'b00001000;
				  4'b1101: out = ~8'b00000100;
		          4'b1110: out = ~8'b00000010;
		          4'b1111: out = ~8'b00000001;
	      endcase
end

endmodule