📄 reg7202.h
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#define LcdVBPMask 0x0ff000000 // Vertical Back Porch (bit 31:24) mask
// Number of inactive lines at the start of a frame, after VSync period.
// Program to zero on passive displays.
#define LcdTiming2 (Videobase + 0x28) // LCD Timing2 Register
#define LcdPCDMask 0x00000001f // Pixel Clock Divisor (bit 4:0) mask
// Used to specify the frequency of the pixel clock based on the LCD clock (LcdCLK)
// frequency. Pixel clock frequency can range from LcdCLK/2 to LcdCLK/33.
// Pixel Clock Frequency = LcdCLK/(PCD+2).
#define LcdPCSMask 0x000000020 // Pixel Clock Source (bit 5) mask
#define LcdPCSDmaClk 0x000000000 // 0 - Video DMA bus clock
#define LcdPCSVGAClk 0x000000020 // 1 - VGA clock
#define LcdACBMask 0x0000007c0 // AC Bias Pin Frequency (bit 10:6) mask
// Number of line clocks to count before toggling the AC Bias pin. This pin is used to
// periodically invert the polarity of the power supply to prevent DC charge build-up within
// the display.
// Program to value required minus 1.
#define LcdIVSMask 0x000000800 // Invert VSync (bit 11) mask
#define LcdIVSactHigh 0x000000000 // 0 - LcdFP pin is active HIGH and inactive LOW.
#define LcdIVSactLow 0x000000800 // 1 - LcdFP pin is active LOW and inactive HIGH.
#define LcdIHSMask 0x000001000 // Invert Hsync (bit 12) mask
#define LcdIHSatciveHigh 0x000000000 // 0 - LcdLP pin is active HIGH and inactive LOW.
//#define LcdIHSatciveHigh 0x000001000 // 1 - LcdLP pin is active LOW and inactive HIGH.
#define LcdIPCMask 0x000002000 // Invert Pixel Clock (bit 13) mask
#define LcdIPCRisingEdge 0x000000000 // 0 - Data is driven on the LCD抯 data lines on the rising-edge of LcdCP.
//#define LcdIPCRisingEdge 0x000002000 // 1 - Data is driven on the LCD抯 data lines on the falling-edge of LcdCP.
#define LcdIEOMask 0x000004000 // Invert Output Enable (bit 14) mask
#define LcdIEOactiveHigh 0x000000000 // 0 - LcdAC pin is active HIGH in TFT mode
#define LcdIEOactiveLow 0x000004000 // 1 - LcdAC pin is active LOW in TFT mode.
#define LcdSLVMask 0x000008000 // Slave mode (bit 15) mask
#define LcdSLVenable 0x000008000 // Slave (or genlock) LCD to VGA video. The HSync and VSync are locked to the VGA
// timing generator. The LCD horizontal timing must be carefully programmed if sharing
// DMA data
#define LcdCPLMask 0x00fff0000 // Clocks Per Link (bit 25:16) mask
// This field specifies the number of actual clocks to the LCD panel on each line. This the
// number of pixels per line divided by either 1 (TFT), 4 or 8 (for mono passive), 2 2 / 3 (for
// color passive), minus one..
// Table 11-5: LCD Controller Bit Fields
#define VgaStatus (Videobase + 0x44) // VGA status Register
#define VgaStLFUFMask 0x01 // FIFO underflow status mask (bit 0)
#define VgaStLFUF 0x01 // FIFO underflow status
#define VgaStLNextMask 0x02 // VGA Next base address update status mask (bit 1)
#define VgaStLNext 0x02 // VGA Next base address update status=20
#define VgaStVCompMask 0x04 // Virtical compare interrupt mask (bit 2)
#define VgaStVComp 0x04 // Virtical compare interrupt
#define VgaStLDoneMask 0x08 // VGA Done frame status mask (bit 3)
#define VgaStLDone 0x08 // VGA Done frame status
#define VgaStatusMask (Videobase + 0x48) // VGA mask Mask Register
#define VgaSMskLFUFMask 0x01 // FIFO underflow mask mask (bit 0)
#define VgaSMskLFUF 0x01 // FIFO underflow mask
#define VgaSMskLNextMask 0x02 // VGA Next base address update mask mask (bit 1)
#define VgaSMskLNext 0x02 // VGA Next base address update mask=20
#define VgaSMskVCompMask 0x04 // Virtical compare interrupt mask (bit 2)
#define VgaSMskVComp 0x04 // Virtical compare interrupt
#define VgaSMskLDoneMask 0x08 // VGA Done frame mask mask (bit 3)
#define VgaSMskLDone 0x08 // VGA Done frame mask
#define VgaInt (Videobase + 0x4c) // VGA Interrupt Register
#define VgaIntLFUFMask 0x01 // FIFO underflow interrupt mask (bit 0)
#define VgaIntLFUF 0x01 // FIFO underflow interrupt
#define VgaIntLNextMask 0x02 // VGA Next base address update interrupt mask (bit 1)
#define VgaIntLNext 0x02 // VGA Next base address update interrupt=20
#define VgaIntVCompMask 0x04 // Virtical compare interrupt mask (bit 2)
#define VgaIntVComp 0x04 // Virtical compare interrupt
#define VgaIntLDoneMask 0x08 // VGA Done frame interrupt mask (bit 3)
#define VgaIntLDone 0x08 // VGA Done frame interrupt
#define VgaDBAR (Videobase + 0x50) // VGA DMA channel Base Address Register
#define VgaDBARMask 0x03ffffe0 // bit 4:0 - should always be written zero
// bit 25:5 - VGA DMA Channel Base Address Pointer
// 8-word aligned base address in SDRAM of fram buffer
// within off-chip memeory
// bit 31:26 - Undefined
#define VgaDCAR (Videobase + 0x54) // VGA DMA channel Current Address Register
#define VgaDCARMask 0x03ffffe0 // bit 4:0 - undefined
// bit 25:5 - VGA DMA Channel current Address Pointer
// 8-word aligned current address in SDRAM of fram buffer
// currently being displayed.
// bit 31:26 - Undefined
#define VgaTiming0 (Videobase + 0x60) // VGA Timing 0 Register
#define VgaPPLMask 0x0000000fc // Pixels Per Line (bit 7:2) mask
// Number of pixels per line, divided by 16, minus 1
#define VgaHSWMask 0x00000ff00 // Horizontal Sync Pluse Width (bit 15:8) mask
// Number of Pixel clock periods to pulse the clock
// at the end of each line minus 1
#define VgaHFPMask 0x000ff0000 // Horizontal Front Porch (bit 23:16) mask
// Number of pixel clock periods to add to the end of a line transmission
// before line clock is asserted, minus 1
#define VgaHBPMask 0x0ff000000 // Horizontal Back Porch (bit 31:24) mask
// Number of pixel clock periods to add to the beginning of a line transmission
// before first set of pixels is output to the display, minus 1
#define VgaTiming1 (Videobase + 0x64) // VGA Timing 1 Register
#define VgaLPSMask 0x0000003ff // Lines per Screen (bit 9:0) mask
// Number of lines per screen. Program to number of lines required minus 1.
#define VgaVSWMask 0x00000fc00 // Vertical Sync Pulse Width (bit 15:10) mask
// Number of VSync lines. Should be small for passive VGA, but should
// be long enough to re-program the video palette under interrupt
// control, without writing the video palette at the same time as video is
// being displayed. Program to the number of lines required minus one.
#define VgaVFPMask 0x000ff0000 // Vertical Front Porch (bit 23:16) mask
// Number of inactive lines at the end of frame, before VSync period.
// Program to zero on passive displays.
#define VgaVBPMask 0x0ff000000 // Vertical Back Porch (bit 31:24) mask
// Number of inactive lines at the start of a frame, after VSync period.
// Program to zero on passive displays.
#define VgaTiming2 (Videobase + 0x68) // VGA Timing 2 Register
#define VgaIVSMask 0x000000800 // Invert VSync (bit 11) mask
#define VgaIVSneg 0x000000000 // 0 - VSync is a negative edge sync.
#define VgaIVSpos 0x000000800 // 1 - VSync is a positive edge sync.
#define VgaIHSMask 0x000001000 // Invert Hsync (bit 12) mask
#define VgaIHSneg 0x000000000 // 0 - HSync is a negative edge sync.
#define VgaIHSpos 0x000001000 // 1 - HSync is a positive edge sync.
#define VgaCVSMask 0x000002000 // Composite VSync (bit 13) mask
// Output XNOR of HSync and VSync on VSync pin (XOR if IVS is
// set)
#define VgaCHSMask 0x000004000 // Composite HSync (bit 14) mask
// Output AND of HSync and VSync on HSync pin (NAND if IHS is
// set)
#define VgaTiming3 (Videobase + 0x6c) // the timing of the VGA border display
#define VgaHBSMask 0x0000000ff // HBS Horizontal border start (bit 7:0) mask
#define VgaHBEMask 0x00000ff00 // HBE Horizontal border end (bit 15:8 ) mask
#define VgaVBSMask 0x000ff0000 // VBS Vertical border start (bit 23:16) mask
#define VgaVBEMask 0x0ff000000 // VBE Vertical border end (bit 31:24) mask
#define VgaBorder (Videobase + 0x70) // VGA border colour register
#define VgaBorderMask 0x000ffffff // RGB 8:8:8 Border Colour
#define VgaTest videobase + 0x80 //=20
#define VgaTestRsv1 0x000000001 // Reserved (bit 0)
#define THDOMask 0x000000006 // THDO Test VGA data output (bit 2:1) mask
#define THDOnormal 0x000000000 // 00 - LCD data bus outputs normal LCD data
#define THDOundefine 0x000000002 // 01 - Undefined
#define THDOLow4 0x000000004 // 10 - LCD data bus outputs LOW nibble of VGA RGB data
#define THDOHigh4 0x000000006 // 11 - LCD data bus outputs HIGH nibble of VGA RGB data
#define TVDATAMask 0x000000008 // Walking one's pattern used in place of SDRAM data for the VGA
// controller (bit 3)
#define TVDATAenable 0x000000008
#define TLDATAMask 0x000000010 // TLDATA Walking one抯 pattern used in place of SDRAM data for the LCD
// controller (bit 4)
#define TLDATAenable 0x000000010
#define TDACMask 0x000000020 // VGA DAC operation mode (bit 5)
#define TDACnormal 0x000000000 // 0 - normal VGA DAC operation
#define TDACtest 0x000000020 // 1 - test VGA DAC operation: DAC Clock and power down from pins,
// DAC data input from LCD data bus pins
#define TRFMask 0x000000040 // TRF For production test of grayscaler, never write a ?1? to these
// registers in normal use. (bit 6)
#define TCFMask 0x000000080 // TCF For production test of grayscaler, never write a ?1? to these
// registers in normal use. (bit 7)
#define TLRMask 0x000000100 // TLR For production test of grayscaler, never write a ?1? to these
// registers in normal use. (bit 8)
#define TCRMask 0x000000200 // TCR For production test of grayscaler, never write a ?1? to these
// registers in normal use. (bit9)
#define TLCMask 0x000000400 // TLC For production test of grayscaler, never write a ?1? to these
// registers in normal use.(bit 10)
#define TCCMask 0x000000800 // TCC For production test of grayscaler, never write a ?1? to these
// registers in normal use.(bit 11)
#define VgaTestRsv2 0x0fffff000 // Reserved (bit 31:12)
#define LcdPalette (Videobase + 0x400) // LCD Palette registers
#define LcdPalRvs1 0x00000000f // 3 : 0 - Reserved
#define LcdPalRed 0x0000000f0 // 7 : 4 R Red palette data
#define LcdPalRvs2 0x000000f00 // 11: 8 - Reserved
#define LcdPalGreen 0x00000f000 // 15:12 G Green palette data
#define LcdPalRvs3 0x0000f0000 // 19:16 - Reserved
#define LcdPalBlue 0x000f00000 // 23:20 B Blue palette data
#define LcdPalRvs4 0x00f000000 // 31:24 - Reserved
#define VgaPalette (Videobase + 0x800) // VGA Palette registers
#define VgaPalRed 0x0000000ff // 7 : 0 R Red palette data
#define VgaPalGreen 0x00000ff00 // 15: 8 G Green palette data
#define VgaPalBlue 0x000ff0000 // 23:16 B Blue palette data
#define VgaPalRvs 0x0ff000000 // 31:24 - Reserved
#define LcdVgaPal (Videobase + 0xc00) // Combined LCD and VGA palette write-only
// registers
/****************************************************************/
/* IRDA Register MAP */
/****************************************************************/
#define IRbase (0x80011000)
#define IrEnReg IRbase
// Encoder Data Rate Modulation Data
// Selected (Mbit/s) Scheme Interface
/****************************************************************/
/* WDT(WatchDog Timer) ***/
/****************************************************************/
#define WDT_BASE 0x8002b000
#define WDTCTRL (WDT_BASE)
#define WDTSTAT (WDT_BASE + 4)
#define WDTCNT (WDT_BASE + 8)
/****************************************************************/
/* End of WDT(WatchDog Timer) ***/
/****************************************************************/
/****************************************************************/
/* SmartMediaCard ***/
/****************************************************************/
#define SmcBase (0x80016000)
#define SmcCmd (SmcBase) // SmartMedia Card Command Register
#define SmcAdr (SmcBase+0x04) // SmartMedia Card Address Register
#define SmcDataW (SmcBase+0x08) // SmartMedia Card Data Write Register
#define SmcDataR (SmcBase+0x0c) // SmartMedia Card Data Read Register
#define SmcConf (SmcBase+0x10) // SmartMedia Card Configuration Register
#define PwrEnable 0x80000000
#define SafeMargine 0x40
#define SmcEn 0x20
#define ContPgEn 0x10
#define IntrEn 0x08
#define DmaEn 0x04
#define UniqueIdEn 0x02
#define BigCardEn 0x01
#define SmcTime (SmcBase+0x14) // SmartMedia Card Time Register
#define DmaSizeMask 0xf0000000
#define WaitCountMask 0x0f000000
#define W1Bclk 0x00000000
#define W2Bclk 0x01000000
#define W3Bclk 0x02000000
#define W4Bclk 0x03000000
#define W5Bclk 0x04000000
#define W6Bclk 0x05000000
#define W7Bclk 0x06000000
#define W8Bclk 0x07000000
#define W9Bclk 0x08000000
#define W10Bclk 0x09000000
#define W11Bclk 0x0a000000
#define W12Bclk 0x0b000000
#define W13Bclk 0x0c000000
#define W14Bclk 0x0d000000
#define W15Bclk 0x0e000000
#define W16Bclk 0x0f000000
#define ByteCountMask 0x007f0000
#define ByteSet512 0x007f0000
#define HighCountMask 0x00000300
#define H1Bclk 0x00000000
#define H2Bclk 0x00000100
#define H3Bclk 0x00000200
#define H4Bclk 0x00000300
#define LowCountMask 0x00000007
#define L1Bclk 0x0
#define L2Bclk 0x1
#define L3Bclk 0x2
#define L4Bclk 0x3
#define L5Bclk 0x4
#define L6Bclk 0x5
#define L7Bclk 0x6
#define L8Bclk 0x7
//s.y.s 0313 modified
#define SmcStatus (SmcBase+0x1C) // SmartMedia Card Status Register
#define CdIntr 0x80000000
#define CdDetect 0x00000008
#define CdIrq 0x00000004
#define CdDrq 0x00000002
#define CdBusy 0x00000001
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