📄 reg7202.h
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// flag will be cleared. If a match event has occurred, bit[1]
// will be set. For a second event, bit[0] will be set. This
// register is affected by the control register.
#define RtcDV (RTCbase+0x0C) // RTC clock divider=20
// Reads to the register will return only four bits of the clock
// divider output. Bits [3:0] will return bits (14,11, 7, 3) of the
// divider output. Write zero to bit[0] clears this divider.
#define RtcCR (RTCbase+0x10) // RTC control register
// This register enables the interrupt. Bit[1] enables the
// match event interrupt (default disable = 0). Bit[0] enables
// second event interrupt (default disable = 0).
#define RtcTic (RTCbase+0x14) // RTC Tic selection register (RTCTS)
// This register is for production test purposes. Bit[0]
// enables TicCLK32K for 32kHz clock replacement. Bit[1]
// enables TicCLKPCLK for PCLK clock replacement.
#define RtcClk32k (RTCbase+0x18) // TicCLK32K
// This generates 32kHz clock for production test purposes.
#define RtcPclk (RTCbase+0x1C) // TicCLKPCLK
// This generates PCLK clock for production test purposes.
/*****************************************************************/
/* PS/2 Interface controller */
/*****************************************************************/
// jelee
#define PS2base (0x8002C000)
#define PSDATA (PS2base ) // Transmit/Receive data register.
#define PSSTAT (PS2base+0x04) // Internal status register
#define PSCONF (PS2base+0x08) // configuration register
#define PSINTR (PS2base+0x0C) // interrupt/error status and interrupt ACK regsiter
#define PSTDLO (PS2base+0x10) // timing parameter register
#define PSTPRI (PS2base+0x14) // timing parameter register
#define PSTXMT (PS2base+0x18) // timing parameter register
#define PSTREC (PS2base+0x20) // timing parameter register
#define PSPWDN (PS2base+0x3C) // Power-down configuration register
/*****************************************************************/
/* AnalogDigital Converter Interface Controller (AIC) Registers*/
/*****************************************************************/
// jelee
#define ADC_BASE (0x80029000)
#define ADCCR (ADC_BASE+0x00) // ADC control register
#define ADCTPCR (ADC_BASE+0x04) // Touch panel control
#define ADCBACR (ADC_BASE+0x08) // Battery check control
#define ADCSDCR (ADC_BASE+0x0C) // Sound Data control
#define ADCISR (ADC_BASE+0x10) // ADC Interrupt Status
#define ADCTDCSR (ADC_BASE+0x1C) // Tipdown Control/Status
#define ADCDIRCR (ADC_BASE+0x20) // ADC direct control
#define ADCDIRDATA (ADC_BASE+0x24) // ADC direct data read
#define ADCTPXDR0 (ADC_BASE+0x30) // Touch panel data [X1:X0] 1st Read
#define ADCTPXDR1 (ADC_BASE+0x34) // Touch panel data [X3:X2] 1st Read
#define ADCTPYDR0 (ADC_BASE+0x38) // Touch panel data [Y1:Y0] 1st Read
#define ADCTPYDR1 (ADC_BASE+0x3C) // Touch panel data [Y3:Y2] 1st Read
#define ADCTPXDR2 (ADC_BASE+0x40) // Touch panel data [X1:X0] 2nd Read
#define ADCTPXDR3 (ADC_BASE+0x44) // Touch panel data [X3:X2] 2nd Read
#define ADCTPYDR2 (ADC_BASE+0x48) // Touch panel data [Y1:Y0] 2nd Read
#define ADCTPYDR3 (ADC_BASE+0x4C) // Touch panel data [Y3:Y2] 2nd Read
#define ADCMBDATA (ADC_BASE+0x50) // Main battery check data
#define ADCBBDATA (ADC_BASE+0x54) // Backup battery check data
#define ADCSDATA0 (ADC_BASE+0x60) // Sound data
#define ADCSDATA1 (ADC_BASE+0x64) // Sound data
#define ADCSDATA2 (ADC_BASE+0x68) // Sound data
#define ADCSDATA3 (ADC_BASE+0x6C) // Sound data
#define ADCSDATA4 (ADC_BASE+0x70) // Sound data
#define ADCSDATA5 (ADC_BASE+0x74) // Sound data
#define ADCSDATA6 (ADC_BASE+0x78) // Sound data
#define ADCSDATA7 (ADC_BASE+0x7C) // Sound data
#define ADCTSTCR (ADC_BASE+0xA0) // Test control
#define ADCTSTCK (ADC_BASE+0xA4) // Test clock
#define ADCTSTR1 (ADC_BASE+0xA8) // Test register1
#define ADCTSTR2 (ADC_BASE+0xAC) // Test register2
#define ADCTSTR3 (ADC_BASE+0xB0) // Test register3
#define ADCEXTEST (ADC_BASE+0xC0) // Test with External signal
/****************************************************************/
/* Static Memory Interface Registers */
/****************************************************************/
#define BUSC_BASE (0x80003000)
#define BUSCbase (0x80003000)
#define BusCMemCfgGR0 (BUSC_BASE) // Memory Configration Register 0
#define BusCMemCfgR1 (BUSC_BASE+0x04) // Memory Configration Register 1
#define BusCMemCfgR2 (BUSC_BASE+0x08) // Memory Configration Register 2
#define BusCMemCfgR3 (BUSC_BASE+0x0c) // Memory Configration Register 3
#define BusCMemCfgR4 (BUSC_BASE+0x10) // Memory Configration Register 4
#define BusCMemCfgR5 (BUSC_BASE+0x14) // Memory Configration Register 5
// Configuration register format
#define BurstEableMask 0x800 // Burst Enable mask
#define BurEN 0x800 // Burst Enable
#define BurstRwaiteMask 0x780 // Burst read wait state mask
// Value Number of wait states
#define BurRwait3 0x000 // 00 3
#define BurRwait2 0x080 // 01 2
#define BurRwait1 0x100 // 10 1
#define BurRwait0 0x180 // 11 0
#define BurstAwaiteMask 0x078 // Burst normal access wait state mask
// Value Number of wait states
#define BurAwait16 0x000 // 0000 16
#define BurAwait15 0x008 // 0001 15
#define BurAwait14 0x010 // 0010 14
#define BurAwait13 0x018 // 0011 13
#define BurAwait12 0x020 // 0100 12
#define BurAwait11 0x028 // 0101 11
#define BurAwait10 0x030 // 0110 10
#define BurAwait9 0x038 // 0111 9
#define BurAwait8 0x040 // 1000 8
#define BurAwait7 0x048 // 1001 7
#define BurAwait6 0x050 // 1010 6
#define BurAwait5 0x058 // 1011 5
#define BurAwait4 0x060 // 1100 4
#define BurAwait3 0x068 // 1101 3
#define BurAwait2 0x070 // 1110 2
#define BurAwait1 0x078 // 1111 1
#define EXPClkEnMask 0x004 // Expansion clock enable mask
#define EXP_ClkEN 0x004 // Expansion clock enable=20
#define MemWidthMask 0x003 // Values of memory width field defines the memory width
// Value bits of memory access
#define MemWidth32 0x000 // 00 32
#define MemWidth16 0x001 // 01 16
#define MemWidth8 0x002 // 10 8
#define MemWidthRsv 0x003 // 11 reserved
/****************************************************************/
/* LCD & VGA Registers */
/****************************************************************/
#define Videobase (0x80010000)
#define VideoControl (Videobase)
#define LcdEnDisMask 0x00001 // LCD Controller (bit 0) mask
#define LcdEnable 0x00001 // LCD Controller Enabled
#define LcdDisable 0x00000 // LCD Controller Disabled
#define LcdBppMask 0x00006 // LCD Bits Per Pixel (bit 2:1) mask
#define Lcd4bpp 0x00000 // 00 - 4bpp
#define Lcd8bpp 0x00002 // 01 - 8bpp
#define Lcd16bpp 0x00004 // 10 - 16bpp
#define LcdRsv 0x00006 // 11 - Reserved
#define LcdBWMask 0x00008 // LCD Monochrome (bit 3) mask
#define LcdBWColor 0x00000 // 0 - Color operation enabled
#define LcdBWMono 0x00008 // 1 - Monocrome operation only enabled
#define LcdTFTMask 0x00010 // LCD TFT (bit 4) mask
#define LcdSTN 0x00000 // 0 - Passive or STN display operation enabled
#define LcdTFT 0x00010 // 1 - Active or TFT display operation enabled
#define LcdReqMask 0x000e0 // LCD FIFO words request level (bit 7:5) mask
// value number of words
#define LcdReq11 0x00000 // 000 11
#define LcdReq12 0x00020 // 001 12
#define LcdReq13 0x00040 // 010 13
#define LcdReq14 0x00060 // 011 14
#define LcdReq15 0x00080 // 100 15
#define LcdReq16 0x000a0 // 101 16
#define LcdReq17 0x000c0 // 110 17
#define LcdReq18 0x000e0 // 111 18
#define VgaEnMask 0x00100 // VGA Controller Enabled (bit 8) mask
#define VgaDisable 0x00000 // 0 - VGA controller Disabled
#define VgaEnable 0x00100 // 1 - VGA controller Enabled
#define VgaBppMask 0x00600 // VGA Bits Per Pixel (bit 10:9) mask
#define Vga4bpp 0x00000 // 00 - 4bpp
#define Vga8bpp 0x00200 // 01 - 8bpp
#define Vga16bpp 0x00400 // 10 - 16bpp
#define VgaReserved 0x00600 // 11 - Reserved
#define ShareDMAMask 0x00800 // Share DMA Data (bit 11) mask
#define ShareDMAEnable 0x00800 // DMA Data streams for LCD and VGA are shared
#define ShareDMADisable 0x00000 // DMA Data streams for LCD and VGA are not shared
#define BGRMask 0x01000 // Video output (bit 12) mask
#define RGB 0x00000 // 0 - RGB normal video output for both LCD and VGA
#define BGR 0x01000 // 1 - BGR red and blue swapped for both LCD and VGA
#define VgaReqMask 0x0e000 // VGA FIFO words request level (bit 15:13) mask
// value number of words
#define VgaReq11 0x00000 // 000 11
#define VgaReq12 0x02000 // 001 12
#define VgaReq13 0x04000 // 010 13
#define VgaReq14 0x06000 // 011 14
#define VgaReq15 0x08000 // 100 15
#define VgaReq16 0x0a000 // 101 16
#define VgaReq17 0x0c000 // 110 17
#define VgaReq18 0x0e000 // 111 18
#define VgaVCompMask 0x30000 // Generate interrupt at: (bit 17:16) mask
#define VgaVSync 0x00000 // 00 - start of VSync
#define VgaBackPorch 0x10000 // 01 - start of BACK PORCH
#define VgaActVideo 0x20000 // 10 - start of ACTIVE VIDEO
#define VgaFrontPorch 0x30000 // 11 - start of FRONT PROCH
#define LcdVCompMask 0xc0000 // Generate interrupt at: (bit 19:18) mask
#define VgaVSync 0x00000 // 00 - start of VSync
//#define VgaBackPorch 0x40000 // 01 - start of BACK PORCH
//#define VgaActVideo 0x80000 // 10 - start of ACTIVE VIDEO
//#define VgaFrontPorch 0xc0000 // 11 - start of FRONT PROCH
#define VDEMask 0x100000 // Video DAC Enable (bit 20) mask
#define DACDisable 0x000000 // 0 - Video DACs disabled(power down)
#define DACEnable 0x100000 // 1 - Video DACs enabled
#define LcdMono8 0x200000
#define Lcd8bit 0x200000
#define Lcd4bit 0x000000
#define LcdPwr 0x400000
#define LcdBLE 0x800000
#define LcdStatus (Videobase + 0x04) // LCD status Register
#define LcdStLFUFMask 0x01 // FIFO underflow status mask (bit 0)
#define LcdStLFUF 0x01 // FIFO underflow status
#define LcdStLNextMask 0x02 // LCD Next base address update status mask (bit 1)
#define LcdStLNext 0x02 // LCD Next base address update status=20
#define LcdStVCompMask 0x04 // Virtical compare interrupt mask (bit 2)
#define LcdStVComp 0x04 // Virtical compare interrupt
#define LcdStLDoneMask 0x08 // LCD Done frame status mask (bit 3)
#define LcdStLDone 0x08 // LCD Done frame status
#define LcdSMask (Videobase + 0x08) // LCD mask Mask Register
#define LcdSMskLFUFMask 0x01 // FIFO underflow mask mask (bit 0)
#define LcdSMskLFUF 0x01 // FIFO underflow mask
#define LcdSMskLNextMask 0x02 // LCD Next base address update mask mask (bit 1)
#define LcdSMskLNext 0x02 // LCD Next base address update mask=20
#define LcdSMskVCompMask 0x04 // Virtical compare interrupt mask (bit 2)
#define LcdSMskVComp 0x04 // Virtical compare interrupt
#define LcdSMskLDoneMask 0x08 // LCD Done frame mask mask (bit 3)
#define LcdSMskLDone 0x08 // LCD Done frame mask
#define LcdInt (Videobase + 0x0c) // LCD Interrupt Register
#define LcdIntLFUFMask 0x01 // FIFO underflow interrupt mask (bit 0)
#define LcdIntLFUF 0x01 // FIFO underflow interrupt
#define LcdIntLNextMask 0x02 // LCD Next base address update interrupt mask (bit 1)
#define LcdIntLNext 0x02 // LCD Next base address update interrupt=20
#define LcdIntVCompMask 0x04 // Virtical compare interrupt mask (bit 2)
#define LcdIntVComp 0x04 // Virtical compare interrupt
#define LcdIntLDoneMask 0x08 // LCD Done frame interrupt mask (bit 3)
#define LcdIntLDone 0x08 // LCD Done frame interrupt
#define LcdDBAR (Videobase + 0x10) // LCD DMA channel Base Address Register
#define LcdDBARMask 0x03ffffe0 // bit 4:0 - should always be written zero
// bit 25:5 - LCD DMA Channel Base Address Pointer
// 8-word aligned base address in SDRAM of fram buffer
// within off-chip memeory
// bit 31:26 - Undefined
#define LcdDCAR (Videobase + 0x14) // LCD DMA channel Current Address Register
#define LcdDCARMask 0x03ffffe0 // bit 4:0 - undefined
// bit 25:5 - LCD DMA Channel current Address Pointer
// 8-word aligned current address in SDRAM of fram buffer
// currently being displayed.
// bit 31:26 - Undefined
#define LcdTiming0 (Videobase + 0x20) // LCD Timing 0 Register
#define LcdPPLMask 0x0000000fc // Pixels Per Line (bit 7:2) mask
// Number of pixels per line, divided by 16, minus 1
#define LcdHSWMask 0x00000ff00 // Horizontal Sync Pluse Width (bit 15:8) mask
// Number of Pixel clock periods to pulse the clock
// at the end of each line minus 1
#define LcdHFPMask 0x000ff0000 // Horizontal Front Porch (bit 23:16) mask
// Number of pixel clock periods to add to the end of a line transmission
// before line clock is asserted, minus 1
#define LcdHBPMask 0x0ff000000 // Horizontal Back Porch (bit 31:24) mask
// Number of pixel clock periods to add to the beginning of a line transmission
// before first set of pixels is output to the display, minus 1
#define LcdTiming1 (Videobase + 0x24) // LCD Timing 1 Register
#define LcdLPSMask 0x0000003ff // Lines per Screen (bit 9:0) mask
// Number of lines per screen. Program to number of lines required minus 1.
#define LcdVSWMask 0x00000fc00 // Vertical Sync Pulse Width (bit 15:10) mask
// Number of VSync lines. Should be small for passive LCD, but should
// be long enough to re-program the video palette under interrupt
// control, without writing the video palette at the same time as video is
// being displayed. Program to the number of lines required minus one.
#define LcdVFPMask 0x000ff0000 // Vertical Front Porch (bit 23:16) mask
// Number of inactive lines at the end of frame, before VSync period.
// Program to zero on passive displays.
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