📄 reg7202.h
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#define Scn11LineMask 0x001 // (bit 0)
#define Scn11LineYes 0x000 // 0 = 1st line will be scanned
#define Scn11LineNo 0x001 // 1 = no scan
#define KBTicIn (KBbase+0x08)
#define Press1Mask 0x080 // (bit 7)
#define Press1KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press1KeyNo 0x080 // 1 = no Press
#define Press2KeyMask 0x040 // (bit 6)
#define Press2KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press2KeyNo 0x040 // 1 = no Press
#define Press3KeyMask 0x020 // (bit 5)
#define Press3KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press3KeyNo 0x020 // 1 = no Press
#define Press4KeyMask 0x010 // (bit 4)
#define Press4KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press4KeyNo 0x010 // 1 = no Press
#define Press5KeyMask 0x008 // (bit 3)
#define Press5KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press5KeyNo 0x008 // 1 = no Press
#define Press6KeyMask 0x004 // (bit 2)
#define Press6KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press6KeyNo 0x004 // 1 = no Press
#define Press7KeyMask 0x002 // (bit 1)
#define Press7KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press7KeyNo 0x002 // 1 = no Press
#define Press8KeyMask 0x001 // (bit 0)
#define Press8KeyYes 0x000 // 0 = 1st Key be Pressned
#define Press8KeyNo 0x001 // 1 = no Press
#define KBVr0 (KBbase+0x0c)
#define KbScn01VMask 0x0ff000000 // 1st column scanin value
#define KbScn02VMask 0x000ff0000 // 2nd column scanin value
#define KbScn03VMask 0x00000ff00 // 3th column scanin value
#define KbScn04VMask 0x0000000ff // 4th column scanin value
#define KBVr1 (KBbase+0x10)
#define KbScn11VMask 0x0ff000000 // 5th column scanin value
#define KbScn12VMask 0x000ff0000 // 6th column scanin value
#define KbScn13VMask 0x00000ff00 // 7th column scanin value
#define KbScn14VMask 0x0000000ff // 8th column scanin value
#define KBVr2 (KBbase+0x14)
#define KbScn21VMask 0x0ff000000 // 9th column scanin value
#define KbScn22VMask 0x000ff0000 // 10th column scanin value
#define KbScn23VMask 0x00000ff00 // 11th column scanin value
#define KbScn24VMask 0x0000000ff // 12th column scanin value
#define KBSr (KBbase+0x18) // This is a 2-bit readable register=20
// that indicates whether a keyboard interrupt has occurred.=20
// The interrupt and the KBSR bit are cleared=20
// after the CPU reads KBSR. The KBSR bit is set=20
// when the key buffer is full, or when the key is pressed=20
// in powerdown mode (keyboard disabled).
#define KbWakeUpMaks 0x02 // Wake up state: (bit 1)
#define KbKeyPressNo 0x00 // 0 = no key pressed in powerdown mode
#define KbKeyPressYes 0x01 // 1 = key pressed in powerdown mode
#define KbBuffFullMask 0x01 // Interrupt state Key bufferstate: (bit 0)
#define KbBuffFullNo 0x00 // 0 = key buffer is not full
#define KbBuffFullYes 0x01 // 1 = key buffer is full
#define KBTClk (KBbase + 0x1c) // This is a virtual register, used to
// generate TIC CLK in test mode.
/****************************************************************/
/* The Programmable Input /Output module (PIO).Registers */
/****************************************************************/
// modified by jelee 010209
#define PIObase (0x80023000)
#define PioADR (PIObase + 0x00) // The following user registers are provided:
#define PioBDR (PIObase + 0x20) // P[A,B,C,D]DR Data Register.=20
#define PioCDR (PIObase + 0x40) // Values written to this 8-bit read/write register will be
#define PioDDR (PIObase + 0x60) // output on port [A,B,C,D] pins if the corresponding data direction bits
#define PioEDR (PIObase + 0x80) // output on port [A,B,C,D] pins if the corresponding data direction bits
// are set HIGH (port output). Values read from this register reflect the
// external state of port [A,B,C,D] not necessarily the value written to it.
// All bits are cleared by a system reset.
#define PioADDR (PIObase + 0x04) // Port [A,B,C,D] Data Direction Register. Bits set in this 8-bit read/
#define PioBDDR (PIObase + 0x24) // write register will select the corresponding pin in port [A,B,C,D] to
#define PioCDDR (PIObase + 0x44) // become an input, clearing a bit sets the pin to output. All bits are set
#define PioDDDR (PIObase + 0x64) // by a system reset.
#define PioEDDR (PIObase + 0x84) // by a system reset.
#define PioAIM (PIObase +0x08) // Interrupt Mask Register. Bits set in this 8-bit read/write register will
#define PioBIM (PIObase +0x28) // select the corresponding pin to become an interrupt source. All bits
#define PioCIM (PIObase +0x48) // are cleared by a system reset.
#define PioDIM (PIObase +0x68)
#define PioEIM (PIObase +0x88)
#define PioAIS (PIObase + 0x0c) // Interrupt Status Register. Values in this 8-bit read-only register
#define PioBIS (PIObase + 0x2c) // represents that the interrupt requests are pending on corresponding
#define PioCIS (PIObase + 0x4c) // pins. All bits are cleared by a system reset.
#define PioDIS (PIObase + 0x6c)
#define PioEIS (PIObase + 0x8c)
#define PioAIE (PIObase + 0x10) // Edge Mode Register. Bits set in this 8-bit read/write register will
#define PioBIE (PIObase + 0x30) // select the corresponding pin to become an edge mode interrupt
#define PioCIE (PIObase + 0x50) // source. All bits are cleared by a system reset.
#define PioDIE (PIObase + 0x70)
#define PioEIE (PIObase + 0x90)
#define PioAIC (PIObase +0x14) // Clear Register. Bits set in this 8-bit write-only register will clear the
#define PioBIC (PIObase +0x34) //stored interrupt request of corresponding bit in edge mode. All bits
#define PioCIC (PIObase +0x54) //are automatically cleared after written.
#define PioDIC (PIObase +0x74)
#define PioEIC (PIObase +0x94)
#define PioAIP (PIObase +0x18) // Polarity Register. Bits set in this 8-bit read/write register will select
#define PioBIP (PIObase +0x38) // the corresponding pin to become an active LOW mode interrupt
#define PioCIP (PIObase +0x58) // source. All bits are cleared by a system reset. After accessing this
#define PioDIP (PIObase +0x78) // register, the Edge Mode register should be cleared with the Clear
#define PioEIP (PIObase +0x98) // register.
// 7202 only
#define PioAmuxctl (PIObase +0x1C)
#define PioBmuxctl (PIObase +0x3C)
#define PioCmuxctl (PIObase +0x5C)
#define PioDmuxctl (PIObase +0x7C)
#define PioEmuxctl (PIObase +0x9C)
#define PioTictMDR (PIObase +0xA0)
#define PioAmuxsel (PIObase +0xA4)
#define PioSwap (PIObase +0xA8)
/****************************************************************/
/* Interrupt Control Registers */
/****************************************************************/
#define INTC_BASE 0x80024000 //IER
#define INTC_ENAR (INTC_BASE) //IER
#define IntEnR (INTC_BASE) //IER
#define INTC_STAT (INTC_BASE+0x4) //ISR
#define IntStatusR (INTC_BASE+0x4)//ISR
#define INTC_VEC (INTC_BASE+0x8) //IVR
#define INTC_VTAB (INTC_BASE+0x10) //SVR0
#define INTC_IDR (INTC_BASE+0x90) //IDR
#define INTC_PRI0 (INTC_BASE+0x94) //PSR0
#define INTC_PRI1 (INTC_BASE+0x98) //PSR1
#define INTC_PRI2 (INTC_BASE+0x9c) //PSR2
#define INTC_PRI3 (INTC_BASE+0xa0) //PSR3
#define INTC_PRI4 (INTC_BASE+0xa4) //PSR4
#define INTC_PRI5 (INTC_BASE+0xa8) //PSR5
#define INTC_PRI6 (INTC_BASE+0xac) //PSR6
#define INTC_PRI7 (INTC_BASE+0xb0) //PSR7
#define INTC_TER (INTC_BASE+0xc0) //??
#define INTC_TIR (INTC_BASE+0xc4) //??
/****************************************************************/
/* Timer Registers */
/****************************************************************/
#define TIMERbase 0x80025000
#define TM0_BASE (TIMERbase)
#define TM0_PERIOD (TM0_BASE+0x00)
#define TM0_COUNT (TM0_BASE+0x08)
#define TM0_CTRL (TM0_BASE+0x10)
#define TM0_TEST (TM0_BASE+0x14)
#define TM1_BASE (TIMERbase+0x20)
#define TM1_PERIOD (TM1_BASE+0x00)
#define TM1_COUNT (TM1_BASE+0x08)
#define TM1_CTRL (TM1_BASE+0x10)
#define TM1_TEST (TM1_BASE+0x14)
#define TM2_BASE (TIMERbase+0x40)
#define TM2_PERIOD (TM2_BASE+0x00)
#define TM2_COUNT (TM2_BASE+0x08)
#define TM2_CTRL (TM2_BASE+0x10)
#define TM2_TEST (TM2_BASE+0x14)
#define TIMER_BASE (TIMERbase+0x60)
#define TIMER_CTRL (TIMERbase+0x60)
#define TIMER_STATUS (TIMERbase+0x64)
#define TIMER_TIC (TIMERbase+0x68)
#define TIMER_DUMMY (TIMERbase+0x7c)
#define TIMER64_LOW (TIMERbase+0x80)
#define TIMER64_HIGH (TIMERbase+0x84)
#define TIMER64_CTRL (TIMERbase+0x88)
#define TIMER64_TEST (TIMERbase+0x8c)
// Bit Description for TMx_CTRL REG
#define TM_START 0x1
#define TM_REPEAT 0x2
#define TM_RESET 0x4
// Bit Description for TIMER_CTRL REG
#define ENABLE_TM0_INTR 0x1
#define ENABLE_TM1_INTR 0x2
#define ENABLE_TM2_INTR 0x4
#define TIMER_POWER_ON 0x8
// Bit Description for TIMER_STATUS REG
#define TIMER_TM0_INTR 0x1
#define TIMER_TM1_INTR 0x2
#define TIMER_TM2_INTR 0x4
#define TIMER_TM64_INTR 0x8
/****************************************************************/
/* Synchronous Serial Interface Registers */
/****************************************************************/
#define SPIbase (0x80015000)
#define SpiCtrlR (SPIbase) // SPI control register
#define SpiRateMask 0x40 // DATA RATE These bits select the baud rate of the SPICLK based on
// divisions of the system clock. The master clock for the
// SPIMMC is PCLK.The bits are encoded as:
#define SpiRateBypass 0x00 // 0 = bypass
#define SpiRateDiv2 0x40 // 1 = Divide by 2
#define SpiCSMask 0x20 // This bit is Chip select signal. In order to communicate external
// device(MMC), CP asserts 0 in this bit.
#define SpiCSEnable 0x00 // 0 = when CP can exchange data with external device (MMC)
#define SpiCSDisable 0x20 // 1 = when CP cannot exchange data with external device
// (MMC)
#define SpiXmodeMask 0x10 // XCHMODE This bit determines the direction of transfer
#define SpiXSend 0x00 // 0 = when CP have valid data to send to MMC (send mode)
#define SpiXRcv 0x10 // 1 = when CP have valid data to receive from MMC (receive
// mode)
#define SpiTstModeMask 0x08 // TestMode When TestMode bit is set, SPI-MMC block is in TIC mode.
// When Tic mode, the operation of the SPI-MMC is same in
// normal mode except that Clock source is not PCLK but TCLK
// which is made in the block.
#define SpiTstNorm 0x00 // 0 = Normal operation
#define SpiTstTic 0x08 // 1 = The SPI-MMC block is in TIC mode
#define SpiLoopMask 0x04 // When set, this bit selects the local loopback operation. The
// transmitter output is internally connected to the receiver input.
// When in loopback mode, the operation of SPI-MMC block is
// same in normal mode except MISO is internally connected MOSI.
#define SpiLoopDis 0x00 // 0 = Normal operation
#define SpiLoopEn 0x04 // 1 = The SPI-MMC block is in loopback mode
#define SpiMasterMask 0x02 // SPIEN This bit enables the SPIMMC. The enable should be asserted
// before initiating an exchange and should be negated after the
// exchange is complete. When the SPIEN bit is cleared,
// consumes minimal power.
#define SpiMasterDis 0x00 // 0 = SPI master disable
#define SpiMasterEn 0x02 // 1 = SPI master enable
#define SpiXCHMask 0x01 // This bit triggers the state machine to generate clocks at the
// selected bit rate.
#define SpiXchEn 0x01 // 1 = Initiate exchange
#define SpiXchDis 0x00 // 0 = No exchange occurs
#define SpiStatR (SPIbase+0x04) // SPI status register
#define SpiTxEmpMask 0x80
#define SpiTxEmp 0x80 // empty This bit is set when TX data buffer is empty. If TX empty goes
// HIGH, a serial peripheral interrupt is generated. Clearing the
// TX empty bit is accomplished by reading the SPISR.
#define SpiXDoneMask 0x40 // XCHDONE=20
#define SpiXDone 0x40 // This bit is set when exchange is completed between CP and
// MMC. If XCHDONE bit goes HIGH, a serial peripheral
// interrupt is generated. Clearing the XCHDONE bit is
// accomplished by reading the SPISR.
#define SpiRxFullMask 0x20
#define SpiRxFull 0x20 // RX full This bit is set when RX data buffer is full. If RX full bit goes
// HIGH, a serial peripheral interrupt is generated. Clearing the
// RX full bit is accomplished by reading the SPISR.
#define SpiStatRsv 0x1f
#define SpiXcnt (SPIbase+0x08) // Number of exchange data
#define SpiTx (SPIbase+0x0c) // TX data buffer (8*8 bits)
#define SpiRx (SPIbase+0x10) // RX data buffer (8*8 bits)
#define SpiTstR1 (SPIbase+0x14) // SPI test register1
#define SpiTstR2 (SPIbase+0x18) // SPI test register2
#define SpiRstR (SPIbase+0x1c) // SPI reset register
#define SpiReset 0x00 // RESET When CP writes 0 to this location, all registers and counters of
// the SPI-MMC block are cleared.
#define SpiDmmyR (SPIbase+0x20) // Dummy R Does not exist Test clock generation
#define SpiTic (SPIbase+0x24) // TIC register
/****************************************************************/
/* Real Time Clock Registers */
/****************************************************************/
#define RTCbase (0x80028000)
#define RtcDR RTCbase // RTC data register (RTCDR)
// Writing to this 32-bit register will load the counter.
// A read will give the current value of the counter.
#define RtcMR (RTCbase+0x04) // RTC match register (RTCMR)
// Writing to this 32-bit register will load the match register.
// This value can also be read back.
#define RtcS (RTCbase+0x08) // RTC status (RTCS)
// When performing a read from this location the interrupt
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