reg7202.h

基于ARM核的HMS7202

/*
 * Copyright (c) 2000 Hyundai Electronics, Ltd. All rights reserved.
 */

/****************************************************************
 *
 *	reg7202.h
 *
 ****************************************************************/

#ifndef __reg_h
#define __reg_h

/****************************************************************/
/*  Internal SRAM Area											*/ 
/****************************************************************/
#define ISRAM_BASE 0x7f000000
#define ISRAM_SIZE 0x800

/****************************************************************/
/*   SDRAM Controller Registers									*/
/****************************************************************/
#define SDRAM_BASE	0x40000000
#define SDRAMC_BASE	0x80000000
#define SDRAMCTRL	SDRAMC_BASE
#define SDRAMREF	(SDRAMC_BASE + 4)
#define SDRAMWBF	(SDRAMC_BASE + 8)
#define SDRAMWAIT	(SDRAMC_BASE + 0xc)
						// 	the quad word merging write buffer.
						//	Timer value	BCLK ticks between time_out
						//		0 	- Time_out disable
						//		1 	- 2
						//		2	- 4
						//		3	- 8
						//		4	- 16
						//		5	- 32
						//		6	- 64
						//		7	- 128

/****************************************************************/
/*   Power management Registers									*/
/****************************************************************/

#define PMUbase			0x80001000
#define	PmuMode		(PMUbase)		// PMU mode register
#define	PmuInit			0x04		// Initialisation mode
#define	PmuRun			0x01		// Run mode
#define	PmuSlow			0x00		// Slow mode
#define	PmuIdle			0x02		// Idle mode
#define	Pmusleep		0x03		// Sleep mode
#define	PmuDsleep		0x07		// Deep Sleep mode

#define PmuID			(PMUbase+0x10)	// read only reg returns chip revision ID
						// ARM7202 ==>  0x00720200
#define PmuResetStatus		(PMUbase+0x20)	// status information on power on reset
						// and PLL status
#define PmuPORMask		0x0001		// POR status mask
#define PmuNoPOR		0x0000		// POR since last cleared
#define PmuPOR			0x0001		// No POR since last cleared

#define PmuPLLLCDMask		0x0002		// LCD PLL mask
#define PmuLCDLock		0x0000		// LCD PLL has been locked since last cleared
#define PmuLCDNoLock		0x0002		// LCD PLL has fallede out of locked since last cleared
		
#define PmuPLLCommsMask		0x0004		// Comms PLL mask
#define PmuCommsLock		0x0000		// Comms PLL has been locked since last cleared
#define PmuCommsNoLock		0x0004		// Comms PLL has fallede out of locked since last cleared

#define PmuPLLSystemMask	0x0008		// System PLL mask
#define PmuSystemLock		0x0000		// System PLL has been locked since last cleared
#define PmuSystemNoLock		0x0008		// System PLL has fallede out of locked since last cleared

#define PmuKeyMask		0x0010		// Key Event mask
#define PmuKeyNoON		0x0000		// No ON key event since last cleared
#define PmuKeyON		0x0010		// On key event

#define PmuModemRIMask		0x0020		// Modem Ring Event mask
#define PmuModemRINoON		0x0000		// No Modem Ring Indicate wake-up event since last cleared
#define PmuModemRION		0x0020		// Modem Ring Indicate wake-up event since last cleared

#define PmuRTCMask		0x0040		// RTC Event mask
#define PmuRTCNoON		0x0000		// No RTC calender wake-up event since last cleared
#define PmuRTCON		0x0040		// RTC calender wake-up event since last cleared

#define PmuPwrFailMask		0x0080		// RTC Event mask
#define PmuPwrFailNoON		0x0000		// No Power Fail  event since last cleared
#define PmuPwrFailON		0x0080		// Power Fail event curred since last cleared

#define PmuResetMask		0x0100		// Warm Reset Event mask
#define PmuResetNoON		0x0000		// No Warm Reset event since last cleared
#define PmuResetON		0x0100		// Warm Reset event curred since last cleared

#define PmuWDTResetMask		0x0200		// Warm Reset Event mask
#define PmuWDTResetNoON		0x0000		// No Warm Reset event since last cleared
#define PmuWDTResetON		0x0200		// Warm Reset event curred since last cleared

#define PmuHSyncMask        0x0400     
#define PmuHSyncNoOn        0x0400     
#define PmuHSyncON          0x0400     


#define PmuIntMask		0xf800		// Interrupt mask
#define PmuIntKey		0x0800		// Key event interrupt mask
#define PmuIntRI		0x1000		// Modem RI event interrupt mask
#define PmuIntRTC		0x2000		// RTC event interrupt mask
#define PmuIntPwrFail	0x4000		// Power Fail event interrupt mask
#define PmuIntHSync     0x8000      // Hot Sync 


#define PmuClkCtl		(PMUbase+0x28)	// 
#define PmuPLL3FreqMask		0x0040
#define PmuPLL3Up		0x040		// PLL3 Frequency control is update
						// instantaneously

#define PmuPLL3Mute		0x0080
#define PmuPLL1Freq		0x0100
#define PmuPLL1max		0x100		// VCLK 40Mhz
#define PmuPLL1min		0x000		// VCLK 31.5Mhz
#define PmuPLL1En		0x4000		// PLL1 Enable
#define PmuPLL2En		0x8000		// PLL2 Enable



/****************************************************************/
/*   DMA Control Registers					*/
/****************************************************************/
#define DMAbase			(0x80004000)
#define DMAC_BASE		(0x80004000)

#define DmacADR0		DMAbase		// DMAC 0 Source Address (Buffer 0 Address)
						//  This channel transfers data from External Memory=20
						//  to the Sound Interface block
#define DmacASR			(DMAbase + 0x04)// DMAC 0 Sound Address (Buffer 1 Address)
						//  This channel transfers data from External Memory=20
						//  to Sound Interface block.
						// This value will be automatically reloaded.
#define DmacTNR0 		(DMAbase + 0x08)// DMAC0 Transfer Number (Buffer 0 Transfer Number)
#define DmacTSR			(DMAbase + 0x0C)// DMAC0 Sound Transfer Number (Buffer 1 Transfer Number)
						//  This value will be automatically reloaded.
#define DmacCCR0		(DMAbase + 0x10)		


#define DmacADR1		(DMAbase + 0x14)// DMAC1 Destination Address
						// This value is start address of ICP RX buffer.
#define DmacTNR1		(DMAbase + 0x18)// DMAC1 Transfer Number
#define DmacCCR1		(DMAbase + 0x1C)	
#define Dmac1EnMask		0x01		// DMEN1 (DMAC1 enable bit) (bit 0)
#define Dmac1Disable		0x00		// DMAC1 Disable
#define Dmac1Enable		0x01		// DMAC1 Enable
#define Dmac1ModselMask		0x02		// MODSEL=20
#define Dmac1ModselLow		0x00		// When LOW, transfer from memory toI/O.
#define Dmac1ModselHigh		0x02		// When HIGH, transfer from I/O to memory.

#define Dmac1MskMask		0x04		// MASK (The mask bit of transfer end interrupt for ICP RX buffer)
					// (bit 1)
#define Dmac1MskDis		0x00		// Disable
#define Dmac1MskEn		0x04		// Enable
#define Dmac1Rsv		0x0f8		// eserved bits

#define DmacADR2		(DMAbase + 0x20)// DMAC2 Destination Address
						// This value is the start address of
						// DMA Channel for USB Controller
#define DmacTNR2		(DMAbase + 0x24)// DMAC2 Transfer Number
#define DmacSIZE		(DMAbase + 0x24)// DMAC2 Transfer Number
#define DmacCCR2		(DMAbase + 0x28) 		
#define Dmac2EnMask		0x01		// DMEN2 (DMAC2 enable bit) (bit 0)
#define Dmac2Disable		0x00		// DMAC2 Disable
#define Dmac2Enable		0x01		// DMAC2 Enable
#define Dmac2ModselMask		0x02		// MODSEL=20
#define Dmac2MemRead		0x00		// When LOW, transfer from memory toI/O.
#define Dmac2MemWrite		0x02		// When HIGH, transfer from I/O to memory.

#define Dmac2INTREN		0x04		// MASK (The mask bit of transfer end interrupt for ICP RX buffer)
						// (bit 1)
#define Dmac2MskDis		0x00		// Disable
#define Dmac2MskEn		0x04		// Enable
#define Dmac2Rsv		0x0f8		// eserved bits
//#define DmacIntStatus	(DMAbase + 0x2c)
//#define DMAC_IntUSB		0x8

//#define DMACMode		(DMAbase + 0x3c)
#define DmacOr			(DMAbase + 0x54)
#define DmacEn			0x01
#define DmacDis			0x00
#define DmacPRMMask		0x06
#define DmacRSV			0xffffffff8


//added by s.y.s
#define Dmac0Sound		0x00
#define Dmac0I2S		0x08
#define Dmac0IntBuff1End	0x04
#define Dmac0IntBuff0End	0x02
#define Dmac0Enable		0x01
//




//added by s.y.s
#define DmacFLAGR		(DMAbase + 0x44)
#define Ch3EndInt		0x10
#define Ch2EndInt		0x08
#define Ch1EndInt		0x04
#define Ch0Buff1EndInt		0x02
#define Ch0Buff0EndInt		0x01
//



/****************************************************************/
/*   USB Registers	- New (7202)								*/
/****************************************************************/

#define US_FIFO_SIZE 8

//---- 7202 defined ---------------------------------------
#define USBbase         (0x80012000)

// gctrl
#define USBgctrl 			(USBbase)
#define USBgctrlMask 			0xf
#define USBgctrlDMADis 		0x1
#define USBgctrlRESUMEn 		0x2
#define USBgctrlTRANDis 		0x8
#define USBgctrlWBMode 		0x4

// endpctrl
#define USBendpctrl 		(USBbase+4)
#define USBendpctrlMask 		0x1fffff
#define USBendpctrlEP0En 		0x1
#define USBendpctrlEP0NAK 		0x8
#define USBendpctrlEP0Rst 		0x40000
#define USBendpctrlEP0STALL 	0x4
#define USBendpctrlEP0TXBYTE0 	0x10
#define USBendpctrlEP0TXBYTE1 	0x20
#define USBendpctrlEP0TXBYTE2 	0x40
#define USBendpctrlEP0TXBYTE3 	0x80
#define USBendpctrlEP0TXnRX 	0x2
#define USBendpctrlEP1En 		0x100
#define USBendpctrlEP1NAK 		0x400
#define USBendpctrlEP1RCVEn 	0x800
#define USBendpctrlEP1Rst 		0x80000
#define USBendpctrlEP1STALL 	0x200
#define USBendpctrlEP2En 		0x1000
#define USBendpctrlEP2NAK 		0x4000
#define USBendpctrlEP2Rst 		0x100000
#define USBendpctrlEP2SENDEn 	0x8000
#define USBendpctrlEP2STALL 	0x2000
#define USBendpctrlEP2TXBYTE0 	0x10000
#define USBendpctrlEP2TXBYTE1 	0x20000

// intmask
#define USBintmask 		(USBbase+8)
#define USBintmaskMask 		0x3ff
#define USBintmaskMKep0empty 	0x8
#define USBintmaskMKep0full 	0x2
#define USBintmaskMKep0overflow 	0x4
#define USBintmaskMKep0stall 	0x200
#define USBintmaskMKep1full 	0x10
#define USBintmaskMKep1overflow 	0x20
#define USBintmaskMKep2empty 	0x40
#define USBintmaskMKsetup 		0x1
#define USBintmaskMKsuspend 	0x100
#define USBintmaskMKusbreset 	0x80

// status
#define USBstatus 		(USBbase+0xc)
#define USBstatusMask 			0xffffff
#define USBstatusconrxst 		0x100000
#define USBstatuscontxst 		0x200000
#define USBstatusep0empty 		0x8
#define USBstatusep0full 		0x2
#define USBstatusep0overflow 	0x4
#define USBstatusep0stall 	 	0x200
#define USBstatusep1full 	 	0x10
#define USBstatusep1overflow 	0x20
#define USBstatusep2empty 		0x40
#define USBstatusrv2p01 		0x800
#define USBstatusrvep0 		0x400
#define USBstatusrvep02 		0x1000
#define USBstatusrvep03 		0x2000
#define USBstatusrvep10 		0x4000
#define USBstatusrvep11 		0x8000
#define USBstatusrvep12 		0x10000
#define USBstatusrvep13 		0x20000
#define USBstatusrvep14 		0x40000
#define USBstatusrvep15 		0x80000
#define USBstatusrxfifost 		0x400000
#define USBstatussetup 		0x1
#define USBstatussuspend 		0x100
#define USBstatustxfifost 		0x800000
#define USBstatususbreset 		0x80

// swreset
#define USBswreset 		(USBbase+0x10)
#define USBswresetMask 		0xf
#define USBswresetEnBCLK 		0x8
#define USBswresetSW_CTRL 		0x4
#define USBswresetPWR_MD1 		0x2
#define USBswresetPWR_MD0 		0x1


// dmamask
#define USBdmamask 		(USBbase+0x14)
#define USBdmamaskMask 		0x3
#define USBdmamaskMKdmarx 		0x2