test0330.rpt

用CPLD控制LED、数码管的显示源代码

LC65 -> - - - - - - - - - - - - - * * * | - - - - * * - - | <-- |74373-4:31|Q2
LC66 -> - - - - - - - - - - - - - * - * | - - - - * * - - | <-- |74373-4:31|Q3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:              d:\timer0331\7128slc-15\test0330.rpt
test0330

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                         Logic cells placed in LAB 'G'
        +------------------------------- LC103 |add25:52|STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
        | +----------------------------- LC105 |add25:52|STATMACH:9|:3
        | | +--------------------------- LC101 |add25:52|STATMACH:9|COUN3
        | | | +------------------------- LC97 |add25:52|STATMACH:9|COUN1
        | | | | +----------------------- LC98 |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node1
        | | | | | +--------------------- LC100 |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node2
        | | | | | | +------------------- LC107 |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node3
        | | | | | | | +----------------- LC108 |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node4
        | | | | | | | | +--------------- LC99 |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node5
        | | | | | | | | | +------------- LC102 |fenpin10:30|count5
        | | | | | | | | | | +----------- LC104 |fenpin10:30|count4
        | | | | | | | | | | | +--------- LC109 |fenpin10:30|count3
        | | | | | | | | | | | | +------- LC110 |fenpin10:30|count2
        | | | | | | | | | | | | | +----- LC111 |fenpin10:30|count1
        | | | | | | | | | | | | | | +--- LC112 |fenpin10:30|count0
        | | | | | | | | | | | | | | | +- LC106 |fenpin10:30|:63
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC103-> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- |add25:52|STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC101-> * * * * - - - - - - - - - - - - | - - * - - - * - | <-- |add25:52|STATMACH:9|COUN3
LC97 -> * * * * - - - - - - - - - - - - | - * - - - - * - | <-- |add25:52|STATMACH:9|COUN1
LC98 -> - - - - - - - - - - - - - * - - | - - - - - - * - | <-- |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node1
LC100-> - - - - - - - - - - - - * - - - | - - - - - - * - | <-- |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node2
LC107-> - - - - - - - - - - - * - - - - | - - - - - - * - | <-- |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node3
LC108-> - - - - - - - - - - * - - - - - | - - - - - - * - | <-- |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node4
LC99 -> - - - - - - - - - * - - - - - - | - - - - - - * - | <-- |fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|result_node5
LC102-> - - - - - - - - * * * * * * * * | - - - - - - * - | <-- |fenpin10:30|count5
LC104-> - - - - - - - * * * * * * * * * | - - - - - - * - | <-- |fenpin10:30|count4
LC109-> - - - - - - * * * * * * * * * * | - - - - - - * - | <-- |fenpin10:30|count3
LC110-> - - - - - * * * * * * * * * * * | - - - - - - * - | <-- |fenpin10:30|count2
LC111-> - - - - * * * * * * * * * * - * | - - - - - - * - | <-- |fenpin10:30|count1
LC112-> - - - - * * * * * * * * * * * * | - - - - - - * - | <-- |fenpin10:30|count0

Pin
22   -> - - - - - - - - - * * * * * * * | - - - - - - * - | <-- CLOCK
11   -> - * * * - - - - - - - - - - - - | * * * * - - * * | <-- START
LC123-> - * * * - - - - - - - - - - - - | - * - - - - * - | <-- |add25:52|STATMACH:8|:3
LC32 -> - - - * - - - - - - - - - - - - | - - - - - - * - | <-- |add25:52|STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC22 -> * * * * - - - - - - - - - - - - | - - - - - - * * | <-- |add25:52|STATMACH:9|COUN2
LC21 -> * * * * - - - - - - - - - - - - | - * - - - - * * | <-- |add25:52|STATMACH:9|COUN0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:              d:\timer0331\7128slc-15\test0330.rpt
test0330

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC124 |addr_chose:43|~154~1
        | +----------------------------- LC114 |addr_chose:43|~156~1
        | | +--------------------------- LC117 |add25:52|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
        | | | +------------------------- LC126 |add25:52|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
        | | | | +----------------------- LC115 |add25:52|STATMACH:7|:3
        | | | | | +--------------------- LC116 |add25:52|STATMACH:7|COUN3
        | | | | | | +------------------- LC125 |add25:52|STATMACH:7|COUN2
        | | | | | | | +----------------- LC127 |add25:52|STATMACH:7|COUN1
        | | | | | | | | +--------------- LC122 |add25:52|STATMACH:7|COUN0
        | | | | | | | | | +------------- LC120 |add25:52|STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
        | | | | | | | | | | +----------- LC119 |add25:52|STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
        | | | | | | | | | | | +--------- LC123 |add25:52|STATMACH:8|:3
        | | | | | | | | | | | | +------- LC121 |add25:52|STATMACH:8|COUN3
        | | | | | | | | | | | | | +----- LC118 |add25:52|STATMACH:8|COUN2
        | | | | | | | | | | | | | | +--- LC113 |add25:52|STATMACH:8|COUN1
        | | | | | | | | | | | | | | | +- LC128 |add25:52|STATMACH:8|COUN0
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC117-> - - - - - - - * - - - - - - - - | - - - - - - - * | <-- |add25:52|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC126-> - - - - - * - - - - - - - - - - | - - - - - - - * | <-- |add25:52|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC115-> - - - - - - - - - - - * * * * * | - - - - - - - * | <-- |add25:52|STATMACH:7|:3
LC116-> - - - * * * - * - - - - - - - - | - - * - - - - * | <-- |add25:52|STATMACH:7|COUN3
LC125-> * - - * * * * * - - - - - - - - | - - - - - - - * | <-- |add25:52|STATMACH:7|COUN2
LC127-> - - * * * * * * - - - - - - - - | - * - - - - - * | <-- |add25:52|STATMACH:7|COUN1
LC122-> - * * * * * * * * - - - - - - - | - - - - - - - * | <-- |add25:52|STATMACH:7|COUN0
LC120-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- |add25:52|STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC119-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- |add25:52|STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC121-> - - - - - - - - - - * * * - * - | - - * - - - - * | <-- |add25:52|STATMACH:8|COUN3
LC118-> * - - - - - - - - - * * * * * - | - - - - - - - * | <-- |add25:52|STATMACH:8|COUN2
LC113-> - - - - - - - - - * * * * * * - | - * - - - - - * | <-- |add25:52|STATMACH:8|COUN1
LC128-> - * - - - - - - - * * * * * * * | - - - - - - - * | <-- |add25:52|STATMACH:8|COUN0

Pin
11   -> - - - - * * * * * - - * * * * * | * * * * - - * * | <-- START
LC68 -> * - - - - - - - - - - - - - - - | - - - - - - - * | <-- |addr_chose:43|~162~1
LC78 -> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- |addr_chose:43|~164~1
LC47 -> * - - - - - - - - - - - - - - - | - - * - - - - * | <-- |add25:52|STATMACH:5|COUN2
LC35 -> - * - - - - - - - - - - - - - - | - - * - - - - * | <-- |add25:52|STATMACH:5|COUN0
LC61 -> - - - - * * * * * - - - - - - - | - - - - - - - * | <-- |add25:52|STATMACH:6|:3
LC51 -> * - - - - - - - - - - - - - - - | - - - * - - - * | <-- |add25:52|STATMACH:6|COUN2
LC53 -> - * - - - - - - - - - - - - - - | - - - * - - - * | <-- |add25:52|STATMACH:6|COUN0
LC22 -> * - - - - - - - - - - - - - - - | - - - - - - * * | <-- |add25:52|STATMACH:9|COUN2
LC21 -> - * - - - - - - - - - - - - - - | - * - - - - * * | <-- |add25:52|STATMACH:9|COUN0
LC42 -> * - - - - - - - - - - - - - - - | - - * - - - - * | <-- |add25:52|STATMACH:10|COUN2
LC48 -> - * - - - - - - - - - - - - - - | - - * - - - - * | <-- |add25:52|STATMACH:10|COUN0
LC17 -> * * - - - - - - - - - - - - - - | - * * * * - - * | <-- |countled:28|:36
LC18 -> * * - - - - - - - - - - - - - - | - * * * * - - * | <-- |countled:28|:37
LC20 -> * * - - - - - - - - - - - - - - | - * * * * - - * | <-- |countled:28|:38


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:              d:\timer0331\7128slc-15\test0330.rpt
test0330

** EQUATIONS **

CLOCK    : INPUT;
PULS     : INPUT;
START    : INPUT;

-- Node name is 'led_addr0' 
-- Equation name is 'led_addr0', location is LC067, type is output.
 led_addr0 = LCELL( _EQ001 $  _EQ002);
  _EQ001 =  _LC017 &  _LC018 &  _LC020 &  _LC027 &  _X001
         # !_LC017 & !_LC018 & !_LC020 &  _LC027 &  _X001;
  _X001  = EXP(!_LC017 & !_LC018 & !_LC020);
  _EQ002 = !_LC017 & !_LC018 & !_LC020;

-- Node name is 'led_addr1' 
-- Equation name is 'led_addr1', location is LC056, type is output.
 led_addr1 = LCELL( _EQ003 $  GND);
  _EQ003 =  _LC017 &  _LC018 &  _LC020 &  _LC028 &  _X001
         # !_LC017 & !_LC018 &  _LC020 &  _X001
         # !_LC017 & !_LC018 &  _LC028 &  _X001;
  _X001  = EXP(!_LC017 & !_LC018 & !_LC020);

-- Node name is 'led_addr2' 
-- Equation name is 'led_addr2', location is LC057, type is output.
 led_addr2 = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC017 &  _LC018 &  _LC020 &  _LC030 &  _X001
         # !_LC017 &  _LC018 & !_LC020 &  _X001
         # !_LC017 & !_LC020 &  _LC030 &  _X001;
  _X001  = EXP(!_LC017 & !_LC018 & !_LC020);

-- Node name is 'led_addr3' 
-- Equation name is 'led_addr3', location is LC059, type is output.
 led_addr3 = LCELL( _EQ005 $  GND);
  _EQ005 = !_LC017 & !_LC018 & !_LC020 &  _LC029 &  _X001
         #  _LC018 &  _LC020 &  _LC029 &  _X001
         # !_LC017 &  _LC018 &  _LC020 &  _X001;
  _X001  = EXP(!_LC017 & !_LC018 & !_LC020);

-- Node name is 'led_addr4' 
-- Equation name is 'led_addr4', location is LC064, type is output.
 led_addr4 = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC017 &  _LC018 &  _LC020 &  _LC024 &  _X001
         #  _LC017 & !_LC018 & !_LC020 &  _X001
         # !_LC018 & !_LC020 &  _LC024 &  _X001;
  _X001  = EXP(!_LC017 & !_LC018 & !_LC020);

-- Node name is 'led_addr5' 
-- Equation name is 'led_addr5', location is LC040, type is output.
 led_addr5 = LCELL( _EQ007 $  GND);
  _EQ007 = !_LC017 & !_LC018 & !_LC020 &  _LC025 &  _X001
         #  _LC017 &  _LC020 &  _LC025 &  _X001
         #  _LC017 & !_LC018 &  _LC020 &  _X001;
  _X001  = EXP(!_LC017 & !_LC018 & !_LC020);

-- Node name is 'led_addr6' 
-- Equation name is 'led_addr6', location is LC037, type is output.
 led_addr6 = LCELL( _EQ008 $  GND);
  _EQ008 = !_LC017 & !_LC018 & !_LC020 &  _LC023 &  _X001
         #  _LC017 &  _LC018 &  _LC023 &  _X001
         #  _LC017 &  _LC018 & !_LC020 &  _X001;
  _X001  = EXP(!_LC017 & !_LC018 & !_LC020);

-- Node name is 'LEDT' = '|FEN30:55|:3' 
-- Equation name is 'LEDT', type is output 
 LEDT    = DFFE( _EQ009 $  VCC, !PULS, !START,  VCC,  VCC);
  _EQ009 =  _LC001 &  _LC007 &  _LC014