📄 test0330.rpt
字号:
RESERVED | 16 70 | RESERVED
RESERVED | 17 69 | RESERVED
RESERVED | 18 68 | RESERVED
GND | 19 67 | RESERVED
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | RESERVED
CLOCK | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
led_addr5 | 28 58 | RESERVED
RESERVED | 29 57 | RESERVED
led_addr6 | 30 56 | led5
RESERVED | 31 55 | led2
GND | 32 54 | led1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
l R l l l V R R R G V R l R G R l l l l V
e E e e e C E E E N C E e E N E e e e e C
d S d d d C S S S D C S d S D S d d d d C
_ E _ _ _ I E E E I E _ E E 6 0 4 3 I
a R a a a O R R R N R a R R O
d V d d d V V V T V d V V
d E d d d E E E E d E E
r D r r r D D D D r D D
4 3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\timer0331\7128slc-15\test0330.rpt
test0330
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 3/ 8( 37%) 0/16( 0%) 19/36( 52%)
B: LC17 - LC32 16/16(100%) 2/ 8( 25%) 9/16( 56%) 24/36( 66%)
C: LC33 - LC48 16/16(100%) 3/ 8( 37%) 9/16( 56%) 25/36( 69%)
D: LC49 - LC64 16/16(100%) 4/ 8( 50%) 1/16( 6%) 15/36( 41%)
E: LC65 - LC80 15/16( 93%) 5/ 8( 62%) 5/16( 31%) 18/36( 50%)
F: LC81 - LC96 16/16(100%) 4/ 8( 50%) 0/16( 0%) 18/36( 50%)
G: LC97 - LC112 16/16(100%) 1/ 8( 12%) 0/16( 0%) 20/36( 55%)
H: LC113 - LC128 16/16(100%) 0/ 8( 0%) 16/16(100%) 28/36( 77%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 22/64 ( 34%)
Total logic cells used: 127/128 ( 99%)
Total shareable expanders used: 40/128 ( 31%)
Total Turbo logic cells used: 127/128 ( 99%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 5.09
Total fan-in: 647
Total input pins required: 3
Total fast input logic cells required: 0
Total output pins required: 15
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 127
Total flipflops required: 57
Total product terms required: 380
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 37
Synthesized logic cells: 22/ 128 ( 17%)
Device-Specific Information: d:\timer0331\7128slc-15\test0330.rpt
test0330
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
22 (17) (B) INPUT 0 0 0 0 0 0 7 CLOCK
5 (14) (A) INPUT 0 0 0 0 0 1 4 PULS
11 (5) (A) INPUT 0 0 0 0 0 1 38 START
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\timer0331\7128slc-15\test0330.rpt
test0330
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
45 67 E OUTPUT t 1 1 0 0 4 0 0 led_addr0
37 56 D OUTPUT t 1 1 0 0 4 0 0 led_addr1
36 57 D OUTPUT t 1 1 0 0 4 0 0 led_addr2
35 59 D OUTPUT t 1 1 0 0 4 0 0 led_addr3
33 64 D OUTPUT t 1 1 0 0 4 0 0 led_addr4
28 40 C OUTPUT t 1 1 0 0 4 0 0 led_addr5
30 37 C OUTPUT t 1 1 0 0 4 0 0 led_addr6
9 8 A FF t 0 0 0 2 3 0 5 LEDT
50 75 E OUTPUT t 0 0 0 0 4 0 0 led0
54 83 F OUTPUT t 0 0 0 0 4 0 0 led1
55 85 F OUTPUT t 0 0 0 0 3 0 0 led2
52 80 E OUTPUT t 0 0 0 0 3 0 0 led3
51 77 E OUTPUT t 0 0 0 0 4 0 0 led4
56 86 F OUTPUT t 0 0 0 0 4 0 0 led5
49 73 E OUTPUT t 0 0 0 0 4 0 0 led6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\timer0331\7128slc-15\test0330.rpt
test0330
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 33 C SOFT s t 8 0 0 0 10 0 2 |addr_chose:43|~153~1
- 124 H SOFT s t 8 0 0 0 10 0 2 |addr_chose:43|~154~1
(21) 19 B SOFT s t 8 0 0 0 10 0 2 |addr_chose:43|~155~1
- 114 H SOFT s t 8 0 0 0 10 0 2 |addr_chose:43|~156~1
- 70 E LCELL s t 1 1 0 0 5 0 1 |addr_chose:43|~161~1
- 68 E LCELL s t 1 1 0 0 5 0 1 |addr_chose:43|~162~1
(46) 69 E LCELL s t 1 1 0 0 5 0 1 |addr_chose:43|~163~1
- 78 E LCELL s t 1 1 0 0 5 0 1 |addr_chose:43|~164~1
- 31 B SOFT s t 0 0 0 0 4 0 1 |addr_chose:43|~292~1
- 74 E SOFT s t 0 0 0 0 4 0 1 |addr_chose:43|~293~1
(41) 49 D SOFT s t 0 0 0 0 4 0 1 |addr_chose:43|~294~1
- 58 D SOFT s t 0 0 0 0 4 0 1 |addr_chose:43|~295~1
- 60 D SOFT s t 0 0 0 0 4 0 1 |addr_chose:43|~296~1
- 55 D SOFT s t 0 0 0 0 4 0 1 |addr_chose:43|~297~1
- 71 E SOFT s t 0 0 0 0 4 0 1 |addr_chose:43|~298~1
- 23 B LCELL s t 1 1 0 0 4 1 1 |addr_chose:43|~306~1
(17) 25 B LCELL s t 1 1 0 0 4 1 1 |addr_chose:43|~307~1
(18) 24 B LCELL s t 1 1 0 0 4 1 1 |addr_chose:43|~308~1
(15) 29 B LCELL s t 1 1 0 0 4 1 1 |addr_chose:43|~309~1
- 30 B LCELL s t 1 1 0 0 4 1 1 |addr_chose:43|~310~1
- 28 B LCELL s t 1 1 0 0 4 1 1 |addr_chose:43|~311~1
(16) 27 B LCELL s t 1 1 0 0 4 1 1 |addr_chose:43|~312~1
- 2 A SOFT t 0 0 0 0 2 0 1 |add25:52|STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
- 12 A SOFT t 0 0 0 0 4 0 1 |add25:52|STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(6) 13 A DFFE t 0 0 0 1 6 0 5 |add25:52|STATMACH:4|:3
- 4 A DFFE t 0 0 0 1 7 0 6 |add25:52|STATMACH:4|COUN3 (|add25:52|STATMACH:4|:9)
- 9 A TFFE t 0 0 0 1 4 0 6 |add25:52|STATMACH:4|COUN2 (|add25:52|STATMACH:4|:10)
- 10 A DFFE t 0 0 0 1 7 0 8 |add25:52|STATMACH:4|COUN1 (|add25:52|STATMACH:4|:11)
(8) 11 A TFFE t 0 0 0 1 2 0 8 |add25:52|STATMACH:4|COUN0 (|add25:52|STATMACH:4|:12)
(27) 43 C SOFT t 0 0 0 0 2 0 1 |add25:52|STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
- 39 C SOFT t 0 0 0 0 4 0 1 |add25:52|STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
- 44 C DFFE t 0 0 0 1 5 0 5 |add25:52|STATMACH:5|:3
(25) 45 C DFFE t 0 0 0 1 6 0 5 |add25:52|STATMACH:5|COUN3 (|add25:52|STATMACH:5|:9)
- 47 C TFFE t 0 0 0 1 3 0 5 |add25:52|STATMACH:5|COUN2 (|add25:52|STATMACH:5|:10)
- 34 C DFFE t 0 0 0 1 6 0 7 |add25:52|STATMACH:5|COUN1 (|add25:52|STATMACH:5|:11)
(31) 35 C TFFE t 0 0 0 1 1 0 7 |add25:52|STATMACH:5|COUN0 (|add25:52|STATMACH:5|:12)
- 63 D SOFT t 0 0 0 0 2 0 1 |add25:52|STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
- 62 D SOFT t 0 0 0 0 4 0 1 |add25:52|STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(34) 61 D DFFE t 0 0 0 1 5 0 5 |add25:52|STATMACH:6|:3
- 50 D DFFE t 0 0 0 1 6 0 5 |add25:52|STATMACH:6|COUN3 (|add25:52|STATMACH:6|:9)
(40) 51 D TFFE t 0 0 0 1 3 0 5 |add25:52|STATMACH:6|COUN2 (|add25:52|STATMACH:6|:10)
- 52 D DFFE t 0 0 0 1 6 0 7 |add25:52|STATMACH:6|COUN1 (|add25:52|STATMACH:6|:11)
(39) 53 D TFFE t 0 0 0 1 1 0 7 |add25:52|STATMACH:6|COUN0 (|add25:52|STATMACH:6|:12)
(74) 117 H SOFT t 0 0 0 0 2 0 1 |add25:52|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(80) 126 H SOFT t 0 0 0 0 4 0 1 |add25:52|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(73) 115 H DFFE t 0 0 0 1 5 0 5 |add25:52|STATMACH:7|:3
- 116 H DFFE t 0 0 0 1 6 0 5 |add25:52|STATMACH:7|COUN3 (|add25:52|STATMACH:7|:9)
(79) 125 H TFFE t 0 0 0 1 3 0 5 |add25:52|STATMACH:7|COUN2 (|add25:52|STATMACH:7|:10)
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