test0330.rpt

用CPLD控制LED、数码管的显示源代码

Project Information                       d:\timer0331\7128slc-15\test0330.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/19/2005 13:04:01

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

test0330  EPM7128SLC84-15  3        15       0      127     40          99 %

User Pins:                 3        15       0  



Project Information                       d:\timer0331\7128slc-15\test0330.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

test0330@22                       CLOCK
test0330@45                       led_addr0
test0330@37                       led_addr1
test0330@36                       led_addr2
test0330@35                       led_addr3
test0330@33                       led_addr4
test0330@28                       led_addr5
test0330@30                       led_addr6
test0330@9                        LEDT
test0330@50                       led0
test0330@54                       led1
test0330@55                       led2
test0330@52                       led3
test0330@51                       led4
test0330@56                       led5
test0330@49                       led6
test0330@5                        PULS
test0330@11                       START


Project Information                       d:\timer0331\7128slc-15\test0330.rpt

** FILE HIERARCHY **



|addr_chose:43|
|7449:42|
|74373-4:31|
|fenpin10:30|
|fenpin10:30|lpm_add_sub:65|
|fenpin10:30|lpm_add_sub:65|addcore:adder|
|fenpin10:30|lpm_add_sub:65|addcore:adder|addcore:adder0|
|fenpin10:30|lpm_add_sub:65|altshift:result_ext_latency_ffs|
|fenpin10:30|lpm_add_sub:65|altshift:carry_ext_latency_ffs|
|fenpin10:30|lpm_add_sub:65|altshift:oflow_ext_latency_ffs|
|fenpin125:29|
|fenpin125:29|lpm_add_sub:73|
|fenpin125:29|lpm_add_sub:73|addcore:adder|
|fenpin125:29|lpm_add_sub:73|addcore:adder|addcore:adder0|
|fenpin125:29|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|fenpin125:29|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|fenpin125:29|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|countled:28|
|countled:28|lpm_add_sub:39|
|countled:28|lpm_add_sub:39|addcore:adder|
|countled:28|lpm_add_sub:39|addcore:adder|addcore:adder0|
|countled:28|lpm_add_sub:39|altshift:result_ext_latency_ffs|
|countled:28|lpm_add_sub:39|altshift:carry_ext_latency_ffs|
|countled:28|lpm_add_sub:39|altshift:oflow_ext_latency_ffs|
|add25:52|
|add25:52|statmach:4|
|add25:52|statmach:4|lpm_add_sub:58|
|add25:52|statmach:4|lpm_add_sub:58|addcore:adder|
|add25:52|statmach:4|lpm_add_sub:58|addcore:adder|addcore:adder0|
|add25:52|statmach:4|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|add25:52|statmach:4|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|add25:52|statmach:4|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|add25:52|statmach:8|
|add25:52|statmach:8|lpm_add_sub:58|
|add25:52|statmach:8|lpm_add_sub:58|addcore:adder|
|add25:52|statmach:8|lpm_add_sub:58|addcore:adder|addcore:adder0|
|add25:52|statmach:8|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|add25:52|statmach:8|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|add25:52|statmach:8|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|add25:52|statmach:9|
|add25:52|statmach:9|lpm_add_sub:58|
|add25:52|statmach:9|lpm_add_sub:58|addcore:adder|
|add25:52|statmach:9|lpm_add_sub:58|addcore:adder|addcore:adder0|
|add25:52|statmach:9|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|add25:52|statmach:9|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|add25:52|statmach:9|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|add25:52|statmach:10|
|add25:52|statmach:10|lpm_add_sub:58|
|add25:52|statmach:10|lpm_add_sub:58|addcore:adder|
|add25:52|statmach:10|lpm_add_sub:58|addcore:adder|addcore:adder0|
|add25:52|statmach:10|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|add25:52|statmach:10|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|add25:52|statmach:10|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|add25:52|statmach:7|
|add25:52|statmach:7|lpm_add_sub:58|
|add25:52|statmach:7|lpm_add_sub:58|addcore:adder|
|add25:52|statmach:7|lpm_add_sub:58|addcore:adder|addcore:adder0|
|add25:52|statmach:7|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|add25:52|statmach:7|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|add25:52|statmach:7|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|add25:52|statmach:6|
|add25:52|statmach:6|lpm_add_sub:58|
|add25:52|statmach:6|lpm_add_sub:58|addcore:adder|
|add25:52|statmach:6|lpm_add_sub:58|addcore:adder|addcore:adder0|
|add25:52|statmach:6|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|add25:52|statmach:6|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|add25:52|statmach:6|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|add25:52|statmach:5|
|add25:52|statmach:5|lpm_add_sub:58|
|add25:52|statmach:5|lpm_add_sub:58|addcore:adder|
|add25:52|statmach:5|lpm_add_sub:58|addcore:adder|addcore:adder0|
|add25:52|statmach:5|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|add25:52|statmach:5|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|add25:52|statmach:5|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|fen30:55|
|fen30:55|lpm_add_sub:74|
|fen30:55|lpm_add_sub:74|addcore:adder|
|fen30:55|lpm_add_sub:74|addcore:adder|addcore:adder0|
|fen30:55|lpm_add_sub:74|altshift:result_ext_latency_ffs|
|fen30:55|lpm_add_sub:74|altshift:carry_ext_latency_ffs|
|fen30:55|lpm_add_sub:74|altshift:oflow_ext_latency_ffs|


Device-Specific Information:              d:\timer0331\7128slc-15\test0330.rpt
test0330

***** Logic for device 'test0330' compiled without errors.




Device: EPM7128SLC84-15

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF



Device-Specific Information:              d:\timer0331\7128slc-15\test0330.rpt
test0330

** ERROR SUMMARY **

Info: Chip 'test0330' in device 'EPM7128SLC84-15' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                                              
                  R     R     R     R                    R  R  R     R  R  R  
                  E     E     E     E                    E  E  E     E  E  E  
                  S     S     S     S  V                 S  S  S     S  S  S  
               S  E     E     E     E  C                 E  E  E  V  E  E  E  
               T  R  L  R     R  P  R  C                 R  R  R  C  R  R  R  
               A  V  E  V  G  V  U  V  I  G  G  G  G  G  V  V  V  C  V  V  V  
               R  E  D  E  N  E  L  E  N  N  N  N  N  N  E  E  E  I  E  E  E  
               T  D  T  D  D  D  S  D  T  D  D  D  D  D  D  D  D  O  D  D  D  
             -----------------------------------------------------------------_ 
           /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
 RESERVED | 12                                                              74 | RESERVED 
    VCCIO | 13                                                              73 | RESERVED 
     #TDI | 14                                                              72 | GND 
 RESERVED | 15                                                              71 | #TDO