addr_chose.v

来自「用CPLD控制LED、数码管的显示源代码」· Verilog 代码 · 共 54 行

module addr_chose(a,b,c,d,e,f,g,addr,outio,wei);
input [3:0]a;
input [3:0]b;
input [3:0]c;
input [3:0]d;
input [3:0]e;
input [3:0]f;
input [3:0]g;
input [2:0] addr;
output [3:0] outio;
output [6:0] wei;
reg [3:0] outio;
reg [6:0] wei;
always  
   begin
    if(addr==0)
      begin
      outio=a;
      wei=7'b0000001;
      end
    else if(addr==1)
      begin
      outio=b;
      wei=7'b0000010;
      end
    else if(addr==2)
      begin
      outio=c;
      wei=7'b0000100;
      end
    else if(addr==3)
      begin
      outio=d;
      wei=7'b0001000;
      end
    else if(addr==4)
      begin
      outio=e;
      wei=7'b0010000;
      end
    else if(addr==5)
      begin
      outio=f;
      wei=7'b0100000;
      end
    else if(addr==6)
      begin
      outio=g;
      wei=7'b1000000;
      end
    end
endmodule